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D DIGITAL SIGNAL PROCESSOR
FORMAT CONVERTER P1.2V P2.5V P3.3V
PLASMA AI
SUB-FIELD PROCESSOR IC9901
IC9900 PD1-Mplus DDR SDRAM(128M)
P2.5V
FORMAT CONVERTER/RGB PROCESSOR PLASMA AI/SUB FIELD PROCESSOR/PEAKS DATA DRIVER
PICTURE
P1.2V
OUTPUT DRVCLKU0-U3
R 10bit
R0-R9 CTI/TINT
R 10bit Video DATA 48bit(DA00-DC13,DB14-DC15)
G 10bit I/P FORMAT COLOR
P2.5V G0-G9
CONVERTER CONVERTER CONTRAST G 10bit NEW SUB-FIELD DATA
B 10bit
B0-B9 WB-ADJ PLASMA AI PROCESSOR DRIVER ROMDATA04-15,ROMADDRESS00-20,(UA05-UC15)
B 10bit
P3.3V st-r
SFRST ROMDATA00-03 (DA14,DA15-DC15)
SFVRST
VD VD LATCH DRVCLKD0-D3
FPCLK
HD HD FPDAT0
DCK DCK JTAG FPDAT1 PCK OCK XRST SCL SDA
P3.3V
60MHz P3V_SCL02
TDO,TDI XRST
14 CLK5
OSD_HD
OSD_VD
P3V_SDA02
TMS,TCK 36.6MHz
4 CLK9 XT 1
X9200
IC9502 IC9303
20MHz
13 CLK6 IC9200 RESET
P3.3V
16/32M FLASH MEMORY
P3.3V
84MHz XTN 20
12 CLK7 CLOCK GENE. CE,OE,WE,BYTE
DQ4-DQ15
TO DG5 D5 5 VCC VOUT 4 RESET
LVDS INPUT A0-A19
RE+(LSB) 1
DQ0-DQ3
RE-(LSB) 2
CLKM PRCKI
RD+ 3 LVDS -IN (FREE_RUN) ROMDATA00-03
JTAG DISCHARGE
RD- 4 Low FLASH ROMDATA04-07/ROMADDRESS00-20,-1,CE,OE,WE,BYTE
RA ,RB ,RC ,RD ,RE ,RCLK Voltage CONTROL CONTROL
RCLK+ 6
Differential (LSI58 COMM)
RCLK- 7
Signaling D31 TO C11
RC+ 9
RECEIVER
RC- 10 IC9500 FPGA Control DATA 10bit ODED1,ODED2,CLRD1,CLRD2,PCD1,PCD2,PCD3,PCD4,LED1,LED2
14 DOUTDA8
DATA DRIVER 24bit
RB+ 11 LVDS RECEIVER (DA00-DC07)
Sustain Control DATA 7bit UMH,UML,USH,USL,UEH,NUEL(URH)
RB- 12
SYNC PROCESSING SS PULSE
CONTROL WB ADJ
FPGA 40 DOUTDC15
RA+ 14 CONTROL DRVCLKD0
DISCHARGE CONTROL 3 CLK0P_C1(CLK(0)(+))
INEXCH Scan Control DATA 16bit OC1,OC2,CLK,SIU,SID,SCSU,CPH1,CPH2,(LAT),CEL,(CBK)CSL,CSH,CML,CMH,SC_DRV_RST
RA- 15 FLASH CONTROL SCAN OUT DRVCLKD1
5 CLK1N_C1(CLK(1)(-))
NCS_FPGA FPGA CONTROL SC PULSE
DRVCLKD2
DATA0 42 CLK2P_C1(CLK(2)(+))
OSD DRVCLKD3
OSD_CLKO
ASDIO IIC DRV_RST 44 CLK3N_C1(CLK(3)(-))
K_DONE
OSD_YSI
LVDSbit
LED1
OSD_GI
OSD_RI
OSD_BI
FVSEL
DCLK RESET NRST 46 LE_C1(LED)
SDA
SCL
NCS DRVMUTE PCD1
47 PC1_C1(PCD1)
PCD2
48 PC2_C1(PCD2)
INEXCH
INEXCH 17 ODED1
49 ODE_C1(ODED1)
DRVMUTE CLRD1
DISPEN 18 50 CLR_C1(CLRD)
ALARM
OSD_CLKO
SOS9_CONF
ALARM 19 P5V 53
OSD_YS
IC9011
OSD_G
READY
OSD_R
OSD_B
TP9100
LVDSBIT
READY 21 P5V
FVSEL
TP9010 55
PANEL_STBY_ON 20 Q9044 STB5V STB 3.3V/RESET STB3.3V
IIC_DATA1 23 P3V_SDA1
Q9302 Q9301 1 5VDET
4 VDD VOUT 3
IIC_CLK1 24 P3V_SCL1
STB3.3V_ON
IIC_DATA2 26 STB_SDA02 Q9046 6 CE RESET 1
D32 TO C21
P5V
IIC_CLK2 27 STB_SCL02 Q9050 1 LSI_RST
TXD_PC 1
OSD_CLKO
TXD 29
RXD_PC D9804
STB3.3V IC9001 72 RESET OSD_CLK 23 TP9101 P5V
RXD 30 OSD_HO
XRST 2 XRST OSD_HD 21 3
1 NCS 32k EEPROM OSD_VO LED2
IIC_CONT/C_SEL 31 OSD_VD 20 5 LE_C2(LED)
D9811
2 DATA
IC9007 IC9013 STB_SDA02 5 SDA WP 7 35 EEP_WR_CTL OSD_R 19
OSD_R PCD3
6 PC3_C2(PCD3)
5
D9802
DCDC_ON
ASDI
PROM(FPGA)
P3V_SCL02
IIC SWITCH
STB_SCL02 6 SCL IC9003 OSD_G 18
OSD_G PCD4
7 PC4_C2(PCD4)
6 DCLK P3V_SDA02 OSD_B ODED2
MICOM OSD_B 17 8 ODE_C2(ODED2)
IIC_CONT 14 VCC 1 OSD_YS CLRD2
OSD_YS 16 9 CLR_C2(CLRD)
STB_SCL01
P3V_SCL01 3 2 50 IIC1_SCL DRVCLKU0
IC9002 4