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A B C D E
LA-2251
1 1
2
Compal confidential 2
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with Sis661FX+Sis963L core logic
3
2004-05-17 3
REV:1.0
4 4
Compal Electronics, Inc.
Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-2251 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 17, 2004 Sheet 1 of 47
A B C D E
A B C D E
Compal confidential
File Name :LA-2251 Fan Control
page 7 Intel Northwood/Prescott Processor MIAN CLOCK DDR CLOCK
Thermal Sensor GENERATOR BUFFER
uFCBGA-479/uFCPGA-478 CPU ADM1032AR
1 ICS952013CF ICS93722 1
page 4,5,6
page 7 page 12 page 13
FSB
H_A#(3..31) 533/800MHz H_D#(0..63)
W/O EXT VGA CHIP
CRT Conn. Memory BUS(DDR)
page 17 SiS 661FX DDR-SO-DIMM X2
BANK 0, 1, 2, 3 page 14,15
LVDS Encoder DVL 1.8V BGA 839 pin 2.5V 200MHz DDR-266/333/400
LCD Conn SiS 302ELV 16 page 8,9,10,11
page 17 page
USB1.1 BT/USB KEY
page 29
USB2.0
USB conn x3
3.3V 48MHz page 29
2 MuTIOL 2
TRANSFOMOR LAN`S PHY 1.8V 133MHz 4x Audio Codec AMP & Audio Jack
RJ45 CONN ALC250
page 25 H0013 page 25 RTL8201CL 25
page
page 27 page 28
MDC & BT Conn. RJ11 CONN
page 29
3.3V 33 MHz PCI BUS page 29
SiS 963L AC-LINK
3.3V 24.576MHz
Mini PCI IEEE 1394 CardBus Controller BGA 371 pin Mini-PCI solt
3.3V page 26
socket VIA-VT6301S ENE CB1410
page 26 page 24 page 23 page 18,19,20,21 Primary IDE
HDD
IDSEL:AD17/AD21 IDSEL:AD16 IDSEL:AD20
(PIRQB#,GNT#1/4,REQ#1/4) (PIRQA#,GNT#0,REQ#0) (PIRQA#,GNT#2,REQ#2) ATA-133 Connector page 22
Slot 0
page 23
Secondary IDE
3
CDROM 3
LPC BUS ATA-133 Connectorpage 22
3.3V 33MHz
RTC CKT.
page 18
ENE KB910 VIA VT1211
Power OK CKT.
page 35
LPC K/B CTRL
page 33
Super I/O
page 30
Power On/Off CKT. Touch Pad Int.KBD
page 32 page 32 page 32 PARALLEL FDD
page 31 page 31
EC I/O Buffer BIOS page 34
page 34
4
DC/DC Interface CKT. 4
page 36
Power Circuit DC/DC Compal Electronics, Inc.
Title
page 37,38,39,40,41,42,43,44,45 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-2251 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 17, 2004 Sheet 2 of 47
A B C D E
A
Voltage Rails
Power Plane Description S0-S1 S3 S5 Symbol Note :
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
: means Digital Ground
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.2V The voltage(1.2V) for Processor VID select ON OFF OFF
+1.25VS 1.25V switched power rail for DDR Vtt ON OFF OFF : means Analog Ground
+1.8VALW 1.8V always on power rail ON ON* ON*
+1.8VS 1.8V switched power rail for SIS M661FX NB. ON OFF OFF
+2.5V 2.5V system power rail for DDR ON ON OFF
@ : means just reserve , no build
+2.5VS 2.5V switched power rail for DDR Clock Buffer ON OFF OFF FIR@ : means just build when FIR Module build in .
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+12VALW 12V always on power rail ON ON ON*
RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices
1
DEVICE IDSEL # REQ/GNT # PIRQ 1
NB Internal VGA N/A N/A A
AGP BUS AGP_DEVSEL N/A A
SOUTHBRIDGE AD13 (INT.) N/A N/A
USB AD14 (INT.) N/A E/F/H Board ID Table for AD channel
AC97 AD13 (INT.) N/A C
Vcc 3.3V +/- 5%
ATA 100 AD13 (INT.) N/A A
Ra 100K +/- 5%
ETHERNET AD15 (INT.) N/A D
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
1394 AD16 0 A
0 0 0 V 0 V 0 V
LAN AD19 3 D
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
CARD BUS AD20 2 A
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
Wireless LAN(MINI PCI) AD17/AD21 1/4 B
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
L Note: PLACE CLOSE TO M661FX, 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
USE 10/10 WIDTH/SPACE 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
Board ID PCB Revision
0 0.1
1 0.2
2 0.3
3 0.4
4 1.0
5
6
7
Compal Electronics, Inc.
Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2251 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 17, 2004 Sheet 3 of 47
A
5 4 3 2 1
+CPU_CORE
D D
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
C8
D7
D9
A8
B7
B9
JP25A
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
8 H_A#[3..31] H_D#[0..63] 8
H_A#3 K2 B21 H_D#0
H_A#4 A#3 D#0 H_D#1
K4 B22
H_A#5 A#4 D#1 H_D#2
L6 A23
H_A#6 A#5 D#2 H_D#3
K1 A25
H_A#7 A#6 D#3 H_D#4
L3 C21
H_A#8 A#7 D#4 H_D#5
M6 D22
H_A#9 A#8 D#5 H_D#6
L2 B24
H_A#10 A#9 D#6 H_D#7
M3 C23
H_A#11 A#10 D#7 H_D#8
M4 C24
H_A#12 A#11 D#8 H_D#9
N1 B25
H_A#13 A#12 D#9 H_D#10
M1 G22
H_A#14 A#13 D#10 H_D#11
N2 H21
H_A#15 A#14 D#11 H_D#12
N4 C26
H_A#16 A#15 D#12 H_D#13
N5 D23
H_A#17 A#16 D#13 H_D#14
T1 J21
H_A#18 A#17 D#14 H_D#15
R2 D25
H_A#19 A#18 D#15 H_D#16
P3 H22
H_A#20 A#19 D#16 H_D#17
P4 E24
H_A#21 A#20 D#17 H_D#18
R3 G23
H_A#22 A#21 D#18 H_D#19
T2 F23
H_A#23 A#22 D#19 H_D#20
U1 F24
H_A#24 A#23 D#20 H_D#21
P6 E25
H_A#25 A#24 D#21 H_D#22
U3 F26
H_A#26 A#25 D#22 H_D#23
T4 D26
H_A#27 A#26 D#23 H_D#24
V2 L21
H_A#28 A#27 D#24 H_D#25
R6 G26
H_A#29 A#28 D#25 H_D#26
W1 H24
H_A#30 A#29 D#26 H_D#27
T5 M21
H_A#31 A#30 D#27 H_D#28
U4 L22
A#31 D#28 H_D#29
V3 J24
C
W2
Y1
AB1
A#32
A#33
A#34
Prescott D#29
D#30
D#31
K23
H25
M23
H_D#30
H_D#31
H_D#32
C
A#35 D#32 H_D#33
N22
D#33 H_D#34
8 H_REQ#[0..4] P21
H_REQ#0 D#34 H_D#35
J1 M24
H_REQ#1 REQ#0 D#35 H_D#36
K5 N23
H_REQ#2 REQ#1 D#36 H_D#37
J4 M26
H_REQ#3 REQ#2 D#37 H_D#38
J3 N26
H_REQ#4 REQ#3 D#38 H_D#39
H3 N25
REQ#4 D#39 H_D#40
8 H_ADS# G1 R21
ADS# D#40 H_D#41
P24
D#41 H_D#42
R25
D#42 H_D#43
AC1 R24
R48 AP#0 D#43 H_D#44
V5 T26
@ 62_0402_5% AP#1 D#44 H_D#45
AA3 T25
H_IERR# BINIT# D#45 H_D#46
+CPU_CORE 1 2 AC3 T22
IERR# D#46 H_D#47
T23
R49 51_0402_5% D#47 H_D#48
+CPU_CORE 1 2 U26
D#48 H_D#49
8 H_BR0# H6 U24
BR0# D#49 H_D#50
8 H_BPRI# D2 U23
BPRI# D#50 H_D#51
8 H_BNR# G2 V25
BNR# D#51 H_D#52
8 H_LOCK# G4 U21
LOCK# D#52 H_D#53
V22
D#53 H_D#54
V24
CK_BCLK D#54 H_D#55
12 CK_BCLK AF22 W26
CK_BCLK# BCLK0 D#55 H_D#56
12 CK_BCLK# AF23 Y26
BCLK1 D#56 H_D#57