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5 4 3 2 1
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S06/S07 System Block Diagram
D D
SYSTEM DC/DC
www.hocnghetructuyen.vn Thermal MAX1999 36
Mobile CPU G768D 18 RGB
CRT INPUTS OUTPUTS
CLK GEN Dothan T8 VRAM*4 CONN
13
5V_S5
3V_S5
DCBATOUT
ICS954226 03 C1 Stepping 04.05 MAX651018 LVDS 5V_AUX
LCD 3D3V_AUX
XGA/SXGA+
HOST BUS 400/533MHz 14 SYSTEM DC/DC
VGA OZ824 37
PCI Express Board S-Video INPUTS OUTPUTS
DDR2 PM TV-OUT
NV44M
400/533Mhz Alviso DB 13 DCBATOUT
1D05V_S0
1D5V_S0
11,12 GM RGB
SC486 38
C
LVDS C
GML S-Video
DCBATOUT
1D8V_S3
0D9V_S0
B1 Stepping 06,07,08,09,10
DMI I/F 100MHz
PWR SW
Int OZ2211S 21
PCI BUS Cardbus/1394
MIC In 27 CARDBUS
/Cardreader OZ711MP1
AC'97 AC-Link (OZ601T OPTION) ONE SLOT 21
Ext CODEC 21,22 CARDReader
MIC In 27
ALC655 7 IN 1 CHARGER
26 23
MODEM OZ860
35
LineOut27 MDC Card Mini-PCI 1394*1
B
20 ICH6-M 802.11A/B/G 28 22 INPUTS OUTPUTS
B
MBATA+
18V 4.0A
Speaker27 TPA6017 PCB LAYER DCBATOUT
27 5V_AUX
LAN L1: Signal 1 5V 100mA
RTL8100C(L) XFMR RJ4525
/RTL8110SB(L) 25 L2: VCC CPU DC/DC
24
LPC BUS
USB*3
L3: Signal 2 SC451 39
B2 Stepping
L4: Signal 3
14.15.16.17 INPUTS OUTPUTS
L5: GND
VCC_CORE
KBC XD BIOS
PATA
L6: Signal 4 DCBATOUT
USB NS ENE 0.844~1.3V
3 PORT
33
87381
30 KB3910 4Mb 27A
29 29
A
HDD A
(master)
19 ODD Touch
Serial INT_KB
(slave)
19 Port*1 FIR 31 Pad 32 32 TECHNOLOGY COPR.
31 Title
Document Number
Block Diagram Rev
S06 MAINBOARD A
Date: Thursday, December 16, 2004 Sheet 1 of 45
5 4 3 2 1
5 4 3 2 1
hocnghetructuyen.vn
Alviso Strapping Signals ICS954226 Spread Spectrum ICH6-M Integrated Pull-up
and Configuration page 7 Select page 3
and Pull-down Resistors
ICH6-M EDS 15851 1.5V1
Pin Name Strap Description Configuration
EE_DIN,EE_DOUT, GNT[3:0]
CFG[2:0] FSB Frequency Select 000 = Reserved Pin17/18
D 001 = FSB533 Byte 6b7 Byte 6b6 byte 6b5 Byte 6b4 Spread Mode Spread Amount% Mhz GNT[4]#/GPO[48], GNT[5]#/GPO[17], D
101 = FSB400
011-111 = Reversed 1 0 0 0 Down 0.8 100 GNT[6]#/GPO[16], GPIO[25] ICH6 internal 20K pull-ups
CFG[3:4] Reversed 1 0 0 1 Down 1.25 100 LAD[3:0]#/FB[3:0]#, LAN_RXD[2:0],
CFG5 DMI x2 Select 0 = DMI x2 1 0 1 0 Down 1.75 100 LDRQ[0], LDRQ[1]/GPI[41],PME#,
1 = DMI x4 (Default)
0 = DDR II (Default) 1 0 1 1 Down 2.5 100 PWRBTN#, TP[3]
CFG6 DDR I / DDR II 1 = DDR I
1 1 0 0 Center +-0.3 100 (Default)
CFG7 CPU Strap 0= Reserved
1=Dothan (Default) 1 1 0 1 Center +-0.5 100
ACZ_BITCLK, ACZ_RST#, ACZ_SDIN[2:0], ICH6 internal 20K pull-downs
CFG8 Reversed 1 1 1 0 Center +-0.8 100
ACZ_SDOUT, ACZ_SYNC, DPRSTP#
1 1 1 1 Center +-1.25 100
CFG9 PCI Express Graphics 0=Reverse Lanes DPRSLPVR, EE_CS, SPKR,
Lane reverse option 1=Normal Operation
for layout convenience (Default) PCI Routing USB[7:0][P,N] SATALED# ICH6 internal 15K pull-downs
CFG10 Reversed
IDSEL IRQ REQ/GNT DD[7], DDREQ ICH6 internal 11.5K pull-downs
CFG11 Reversed
OZ711MP1 LAN_CLK ICH6 internal 100K pull-downs
00 = Reserved 25 E 0
CFG[13:12] XOR/ALL Z test
straps
01 = XOR mode enabled
10 = All Z mode enabled
1394
11 = Normal Operation
(Default)
ICH6-M Strapping Options
C C
CFG[14:15] Reversed MiniPCI 21 C 1 REF FUNCTION DEFAULT OPTIONAL OVERRIDE
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled LAN 23 C 2
1 = Dynamic ODT Enabled R7F9 No Reboot NO_STUFF STUFF
(Default)
A16 Swap
CFG17 Reversed R7F8 Override NO_STUFF STUFF
CFG18 GMCH core VCC 0 = 1.05V (Default)
ICH6-M IDE Integrated Series
Select 1 = 1.5V R7F7 Boot BIOS NO_STUFF STUFF
CFG19 CPU VTT Select 0 = 1.05V (Default)
Termination Resistors
1 = 1.2V
CFG20 Reversed DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
SDVO SDVO Present 0 = No SDVO device present DDACK#, IORDY, DA[2:0], DCS1#,
CRTL_DATA (Default)
1= SDVO device present DCS3#, IDEIRQ
Super I/O (PC87381) Strapping Options
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
PinNumber PinName Function
KBC Hardware Strap
BADDR Base Address.
PinNumber PinName Function 2 No pull down(default) - the Index-Data pair at 164Eh-164Fh
B 10 K external pull-down resistor - the Index-Data pair at 2Eh-2Fh1 B
125 A1 High:Enable the internal pull-up resistors on XIOCS [F:0] pins
Low:Disable the internal pull-up resistors on XIOCS [F:0] TRI-STATE Device
No pull-down resistor (default) - normal pin operation
47 TRIS
128 A4 High: Diasble DMPP(Recommended) 10 K external pull-down resistor - floating device pins
Low : Enable DMPP TRIS is set to 0 (by an external pull-down resistor), TEST must be 1
131 A5 High:Enable EMWB(Recommended for application using shared BIOS
XOR Tree Test Mode.
Low:Disable EMWB
No pull-down resistor (default) - normal pin operation
11 GPIO05 High:Test Mode 48 TEST 10 K external pull-down resistor - pins configured as XOR tree.
Low:32KHz clock in normal running(Recommend) When TEST is set to 0 (by an external pull-down resistor),
TRIS must be 1
12 GPIO06 High:Test Mode(KSOUT0~15 become DPLL internal data outputs,
KSO16 becomes internal power-on reset output
Low:Normal operation(Recommended)
105 GPIO20 High:Normal operation(Recommended)
A A
Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0]
andD[7:0}will be controlled by ISP COntroller
TECHNOLOGY COPR.
Title
Document Number
Table of content Rev
S06 MAINBOARD A
Date: Thursday, December 16, 2004 Sheet 2 of 45
5 4 3 2 1
5 4 3 2 1
3D3V_S0 R1 R0402
0 +/-5% 3D3V_S0 FB1 FB L0603 180 Ohm
3D3V_APWR_S0
BC1 BC2 1 2 3D3V_CLKGEN_S0
4.7uF 0.1uF BC3 BC4 BC5 BC6 BC7 BC8 BC9 BC10
10V, Y5V, +80%/-20% * * 16V, Y5V, +80%/-20%
* 10uF 0.1uF
* 0.1uF
* * 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
C0805 C0402 10V, Y5V, +80%/-20%
C0805 C0402 C0402 C0402 C0402 C0402 C0402 C0402
16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%
D D
3D3V_S0 R2
0
R0402
+/-5%
hocnghetructuyen.vn
3D3V_48MPWR_S0
BC11 BC12
4.7uF 0.1uF
* *16V, Y5V, +80%/-20%
U1
C0805 C0402
10V, Y5V, +80%/-20%
3D3V_APWR_S0 37 54
VDDA CPU_STP# PM_STPCPU# 15,39
3D3V_CLKGEN_S0 1 44 RN1 1 4 4P2R0402V CLK_CPU_BCLK 4
VDDPCI CPUT0 33
7 VDDPCI CPUC0 43 2 3 +/-5% CLK_CPU_BCLK# 4
3D3V_S0 21 41 RN2 1 4 4P2R0402V CLK_MCH_BCLK 6
VDDPCIEX CPUT1 33
28 VDDPCIEX CPUC1 40 2 3 +/-5% CLK_MCH_BCLK# 6
34 VDDPCIEX
36 CLK_XDP_CPU 1 TP1
R626 CPUT2_ITP/PCIEXT6 CLK_XDP_CPU#1 TP2
42 VDDCPU CPUC2_ITP/PCIEXC6 35
10K 48
+/-5% VDDREF RN3
ITP_EN 0=PCIEX_6 1=CPU_2_ITP LCDCLK_SS/PCIEX0T 17 2 3 4P2R0402V DREFSSCLK 7
R0402 3D3V_48MPWR_S0 11 18 33 1 4 +/-5%
SS_SEL 0=LCDCLK 1=PCIEX/free running VDD_48 LCDCLK_SS/PCIEX0C DREFSSCLK# 7
Dummy
3.3V PCI clock output PCIEXT1 19 @GM
R6 33 R0402 +/-5% 56 20
C
28
21,43
PCLK_MINI
PCLK_PCM R7 33 R0402 +/-5% 3
PCICLK2/REQ_SEL
PCICLK3
** PCIEXC1
C
3D3V_S0 29 PCLK_KBC R8 33 R0402 +/-5% 4 22 RN4 2 3 4P2R0402V CLK_MCH_3GPLL 7
PCICLK4 PCIEXT2 33
30 PCLK_SIO R9 33 R0402 +/-5% 5 PCICLK5 PCIEXC2 23 1 4 +/-5% CLK_MCH_3GPLL# 7
H/L: 100/96MHz
24 PCLK_LAN R10 33 R0402 +/-5% SS_SEL 9 24 RN5 2 3 4P2R0402V CLK_PCIE_PEG 42
SELPCIEX_LCDCLK#/PCICLK_F1 PCIEXT3 33
55 25 1 4 +/-5%
R12 R13
15 PM_STPPCI#
15 CLK_ICHPCI R11 33 R0402 +/-5% ITP_EN 8
PCI/SRC_STP#
ITP_EN/PCICLK_F0
** PCIEXC3 CLK_PCIE_PEG# 42
10K 10K H/L : CPU_ITP/SRC7 26 @PM
+/-5% +/-5% SATACLKT
SATACLKC 27
R0402 R0402 39 VTT_PWRGD# VTT_PWRGD# 10
Dummy VTT_PWRGD#/PD RN6
PCIEXC4 30 2 3 4P2R0402V CLK_PCIE_ICH# 15
R14 22R0402 +/-5% FS_A 12 31 33 1 4 +/-5%
15 CLK48_ICH USB_48/FS_A PCIEXT4 CLK_PCIE_ICH 15
ITP_EN
SS_SEL RN7 1 4 4P2R0402V 14 32
7 DREFCLK
33 2 3 +/-5% 15
DOT96T * PEREQ2#/PCIEXC5
33
R15 R16
7 DREFCLK# DOT96C * PEREQ1#/PCIEXT5
10K 10K 11,17 SMBC_ICH @GM 46
+/-5% +/-5% SCLK
11,17 B_SMBD_ICH 47 SDATA GND 13
R0402 R0402
*
Dummy BC13 50V, NPO, +/-5% X2_ICS 49 51 DREFSSCLK R17 0 @PM 1D5V_S0
1D05V_S0 C0603 X1_ICS XOUT GND R0603 +/-5%
50 XIN GND 45
2
33pF GND 29
R18 X1 BSEL0 53
1K BSEL1 REF1/FS_C/TEST_SEL
X-14D318MHz 16 FS_B/TEST_MODE GND 2
+/-5% 6
1
GND
*
R0402 BC14 R19 R0402 39 DREFCLK R20 0 @PM 1D5V_S0
Dummy C0603 50V, NPO, +/-5% 475 +/-1% 52 IREF R0603 +/-5%
REF0 GNDA 38
B 4 CPU_SEL0 R21 0 +/-5% R627 2.2K BSEL0 B
R0402 R0402 +/-5% 33pF R22 47R0402 +/-5%
15 CLK_ICH14
R24 FS_C ICS954226
7 MCH_BSEL0 R23 1K+/-5% 2.2K 30 SIO_14M R25 47R0402 +/-5%
R0402 +/-5%
R0402 *internal Pull-Up resistors
Dummy EMI capacitor
**internal Pull-Down resistor
1D05V_S0 BSEL0 R518 22R0402 +/-5% AC_CLK 26
CLK_ICH14 C1 10pF C0402 50V, NPO, +/-5% Dummy
********
R26
1K
To external AC'97 CLK PCLK_PCM C2 10pF C0402 50V, NPO, +/-5% Dummy
+/-5%
R0402 PCLK_MINI C3 10pF C0402 50V, NPO, +/-5% Dummy
Dummy
4 CPU_SEL1 R27 0 +/-5% BSEL1 CLK_PCIE_ICH R28 49.9 R0402 +/-1% CLK_CPU_BCLK R29 49.9 R0402 +/-1% PCLK_KBC C4 10pF C0402 50V, NPO, +/-5% Dummy
R0402 FS_B
R33 CLK_PCIE_ICH# R30 49.9 R0402 +/-1% CLK_CPU_BCLK# R31 49.9 R0402 +/-1% CLK_ICHPCI C5 10pF C0402 50V, NPO, +/-5% Dummy
7 MCH_BSEL1 R32 1K+/-5% 2.2K
R0402 +/-5% DREFSSCLK# R34 49.9 R0402 +/-1% CLK_MCH_BCLK R35 49.9 R0402 +/-1% CLK48_ICH C6 10pF C0402 50V, NPO, +/-5% Dummy
R0402
Dummy DREFSSCLK R36 49.9 R0402 +/-1% @GM CLK_MCH_BCLK# R37 49.9 R0402 +/-1% PCLK_SIO C7 10pF C0402 50V, NPO, +/-5% Dummy
DREFCLK R38 49.9 R0402 +/-1% @GM CLK_MCH_3GPLL R39 49.9 R0402 +/-1% SIO_14M C8 10pF C0402 50V, NPO, +/-5% Dummy
3D3V_S0
DREFCLK# R40 49.9 R0402 +/-1% CLK_MCH_3GPLL# R41 49.9 R0402 +/-1%
A R42 A
10K FS_C FS_B FS_A CPU CLK_PCIE_PEG R43 49.9 R0402 +/-1% @PM
+/-5%
R0402 0 0 0 266M CLK_PCIE_PEG# R44 49.9 R0402 +/-1% @PM
FS_A 0 0 1 133M
0 1 0 200M TECHNOLOGY COPR.
R45 0 1 1 166M
10K 1 0 0 333M Title
+/-5% 1 0 1 100M (Default)
R0402
Dummy
1 1 0 400M
Document Number
Clock Generator Rev
S06 MAINBOARD A
Date: Friday, December 17, 2004 Sheet 3 of 45
5 4 3 2 1
5 4 3 2 1
U2A TP3