74ls48.pdf part of datasheets 74ls48 74ls48.pdf, . Electronic Components Datasheets Various datasheets 74ls48.pdf text manual preview

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SN54/74LS48
BCD TO 7-SEGMENT
DECODER
The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates
and one driver are connected in pairs to make BCD data and its complement BCD TO 7-SEGMENT
available to the seven decoding AND-OR-INVERT gates. The remaining DECODER
NAND gate and three input buffers provide lamp test, blanking input/ripple-
blanking input for the LS48. LOW POWER SCHOTTKY
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive other components.
The relative positive logic output levels, as well as conditions required at the
auxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and / or trailing edge
J SUFFIX
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any
CERAMIC
time when the BI / RBO node is HIGH. Both devices contain an overriding CASE 620-09
blanking input (BI) which can be used to control the lamp intensity by varying 16
the frequency and duty cycle of the BI input signal or to inhibit the outputs. 1