Text preview for : Joybook_DC_Joybook_R48_20100506_092731_R48_schematics.pdf part of . Various Joybook DC Joybook R48 20100506 092731 R48 schematics . Various Joybook_DC_Joybook_R48_20100506_092731_R48_schematics.pdf
Back to : Joybook_DC_Joybook_R48_20 | Home
5 4 3 2 1
CZC Confidential
D
CZC Digital technologies Co.,LTD
Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
Project name: CPL S01 (R48)
3. Annotations & information;
Version: VerC
4. Schematic modify Item and history;
Start Date:JAN 6,2010 5. Power on & off Sequence;
C 6. ACPI Mode Switch Timings;
VerA Release Data:
7. Power On Sequence Map;
8. CLOCK Distribution;
B
Hardware drawing by: Hardware check by: EMI Check by:
Power drawing by: Power check by:
A Manager Sign by: A
CZC Technology zw
Title
<br><br> Size Project Name Rev<br> A4 R48 C<br><br> Date: Thursday, April 22, 2010 Sheet 1 of 56<br> 5 4 3 2 1<br> S45 System Block Ver:A<br> PWR_BTN Board<br><br><br> MB<br> RJ45 Board<br>D DDR3 1GB/512M<br> D<br> QKey & LID Board<br> LVDS SO-DIMM 0<br> DDRIII<br> VGA +V1.5,+V0.75S<br> Madison/Park PCIE X16 Arrandale<br> HDMI<br> SO-DIMM 1<br> DDRIII To RJ45<br> +V1.5,+V0.75S<br><br><br><br> TFT MUX FDI DMI X4<br><br> PWR Switch<br> LVDS PCIE X1 LAN Controller R5538/TPS2231/OZ2709<br> VGA<br> MUX AR8131M<br> VGA<br><br> PCIE X1<br> MUX USB2.0 Express Card<br> HDMI HDMI<br> PCIE X1<br><br> PCIE X1 mini PCIE Card<br> 3G<br>C PCH<br> USB2.0 C<br> HM55/HM57<br> SIM SLOT<br> SATA<br> ODD<br> mini PCIE<br> SATA USB2.0 Card<br> HDD<br> 2.5" R<br> USB AUDIO Board<br> SPI AZALIA LINK Azalia Codec<br> AN12948A<br> ALC662<br> SATA<br> L<br> HP Out<br> BIOS Mic In<br> LPC BUS<br><br> USB2.0<br> USB<br> Port<br>B SPI KB Ctrl & EC B<br> WPC8763L SD/MS/MS Pro CARD<br> USB2.0 Cardreader<br> UB6238N USB<br> EC Code Port<br> +<br> USB2.0 eSATA<br> USB Port<br> KB Matrix<br><br> USB2.0 Camera<br><br><br><br> USB2.0 BT<br> LED<br> TP<br><br><br><br><br>A A<br> CZC Technology zw<br> Title<br><br> <Title><br> Size Project Name Rev<br><br> A4 R48 C<br> Date:<br> Thursday, April 22, 2010 Sheet<br> 2 of<br> 56<br> 5 4 3 2 1<br><br> AC Mode Battery Mode<br> POWER RAIL<br> S0 S1 S3 S4 S5 S0 S1 S3 S4 S5<br> +V3.3AUX ON ON ON ON ON ON ON ON OFF OFF<br> +V5AUX ON ON ON ON ON ON ON ON OFF OFF<br> +V1.5 ON ON ON OFF OFF ON ON ON OFF OFF<br>D D<br> +V0.75S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V5S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V3.3S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V1.8S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +V1.1S ON ON OFF OFF OFF ON ON OFF OFF OFF<br> +Vcore ON ON OFF OFF OFF ON ON OFF OFF OFF<br> GFXCORE ON ON OFF OFF OFF ON ON OFF OFF OFF<br><br><br><br><br> 14.31818MHz 25MHz<br> XTAL XTAL<br>C C<br><br> 133MHz<br> BCLK<br> 133MHz 100MHz<br> BCLK DMI<br> CPU<br> 120MHz<br> DP<br> 100MHz<br> DMI<br> PCH<br> 100MHz<br> Buffered PEG A<br> CK505 100MHz Mode GPU<br> SATA<br><br> 100MHz<br> 96MHz PCIE NEW CARD<br> DOT Mini PCIE SLOT X2<br>B B<br><br> 14.31818MHz 33MHz<br> REF PCI<br> KBC<br> 100MHz<br> PCIE<br><br> LAN<br> 48MHz<br><br><br><br><br> 25MHz<br> XTAL<br>A No stuff A<br><br> CZC Technology zw<br> Title<br> <Title><br><br> Size Project Name Rev<br> A3 R48 C<br><br> Date: Thursday, April 22, 2010 Sheet 3 of 56<br> 5 4 3 2 1<br><br><br><br> Board stack up description<br> Voltage Rails +Vcore:0.75V-1.1V I2C SMB Address PCB Layers<br><br> +VDC Primary DC system power supply(9V-12V)<br> Device Address Hex(W/R) Bus Master Top(Signal1)<br>D D<br> +VCC_core Core/VTT voltage for processor Clock Generator 1101 001x D2H/D3H Ground<br><br> SO-DIMM0 1010 000x 0xA0 SMB_CLK/DATA PCH Signal2<br> +V1.8S 1.8V For PCH CPU<br> SO-DIMM1 1010 010x 0xA4 Signal3 Trace Impedence:50ohm +/-15%<br> +V1.1S 1.05V /1.1V For PCH CPU GPU<br> OZ8805LN 0001 011x 16H/17H EC_I2C_CLK2/DATA2 Power<br> +V0.75S 0.75V DDRIII Termination voltage<br> EC<br> +V1.5S 1.5V for system power Thermal Diode G781 1001 100x 98H/99H EC_I2C_CLK/DATA Signal4<br><br> Ground<br> +V1.5 1.5V power rail for DDRIII<br> Bottom(Signal5)<br><br> +V3.3AUX 3.3V always on power rail<br> +V3.3S 3.3V main power rail<br> +V5AUX 5V always on power rail<br> PCB Layer Difference signal Impedence list<br> +V5S 5V main power rail<br>C C<br> USB signal difference impedence 85ohm<br> LVDS signal difference impedence 85ohm<br> DDRIII signal difference impedence 85ohm<br> Power States DDRIII CLK signal difference impedence 68ohm<br><br> signal PM_SLP_S3#<br> state PM_SLP_S4# +V*AUX +V* +V*S CLOCKS<br> Full ON HIGH ON ON ON ON<br> S1M(Power On Suspend) HIGH ON ON ON LOW Wake up Events<br> S3(Suspend to RAM) HIGH LOW ON ON OFF OFF<br> S4(Suspend to DISK) LOW LOW ON OFF OFF OFF Wake Events State Supported(AC)<br> S5/Soft Off OFF OFF<br> With AC IN LOW LOW ON OFF<br><br> G3<br> With Battery LOW LOW OFF OFF OFF OFF<br> LID switch from EC S3 support<br>B Power Button from EC S3,S4,S5 support B<br> Keyboard from EC No<br> USB device No<br><br> [Option]:ns -- Component marked "ns" is not stuff<br> [Use State]:new --Component Marked "new" is new Materiel.<br><br><br><br> PCB Footprints<br> 3 5 4<br><br> SOT23 SOT23_5<br><br> 1 2 1 2 3<br>A A<br><br> CZC Technology zw<br> Title<br> <Title><br><br> Size Project Name Rev<br> A3 R48 C<br><br> Date: Thursday, April 22, 2010 Sheet 4 of 56<br> 5 4 3 2 1<br><br><br><br><br> +V3.3AUX 13,14,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35<br> +V1.5S 7,16,21,22,28,35,36<br> +V1.5 7,8,10,11,33,35<br> +V1.1S_VTT 7,12,16,17,35,36<br> +V3.3S 9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48<br> U1A<br> +V1.5S_CPU 7<br> PEG_ICOMPI B26 PEG_IRCOMP_R R1 49.9,1%<br> PEG_ICOMPO A26 PEG_RXN[15:0] 41<br> A24 B27 PEG_RXN0<br> 14 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO<br> C23 A25 EXP_RBIAS R2 750 PEG_RXN1<br> 14 DMI_TXN1 DMI_RX#[1] PEG_RBIAS<br> B22 PEG_RXN2<br> 14 DMI_TXN2 DMI_RX#[2]<br> A21 K35 PEG_RXN15 PEG_RXN3<br> 14 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]<br> J34 PEG_RXN14 PEG_RXN4<br> PEG_RX#[1] PEG_RXN13 PEG_RXN5<br> 14 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33<br> D23 G35 PEG_RXN12 PEG_RXN6<br> 14 DMI_TXP1 DMI_RX[1] PEG_RX#[3]<br><br><br><br><br> DMI<br> B23 G32 PEG_RXN11 PEG_RXN7<br> 14 DMI_TXP2 DMI_RX[2] PEG_RX#[4]<br> A22 F34 PEG_RXN10 PEG_RXN8<br> 14 DMI_TXP3 DMI_RX[3] PEG_RX#[5]<br> F31 PEG_RXN9 PEG_RXN9<br> PEG_RX#[6] PEG_RXN8 PEG_RXN10<br>D D24 DMI_TX#[0] PEG_RX#[7] D35 D<br> 14 DMI_RXN0 PEG_RXN7 PEG_RXN11<br> G24 DMI_TX#[1] PEG_RX#[8] E33<br> 14 DMI_RXN1 PEG_RXN6 PEG_RXN12<br> F23 DMI_TX#[2] PEG_RX#[9] C33<br> 14 DMI_RXN2 PEG_RXN5 PEG_RXN13<br> H23 DMI_TX#[3] PEG_RX#[10] D32<br> 14 DMI_RXN3 PEG_RXN4 PEG_RXN14<br> PEG_RX#[11] B32<br> D25 C31 PEG_RXN3 PEG_RXN15<br> 14 DMI_RXP0 DMI_TX[0] PEG_RX#[12] PEG_RXN2<br> F24 DMI_TX[1] PEG_RX#[13] B28 PEG_RXP[15:0] 41<br> 14 DMI_RXP1 PEG_RXN1 PEG_RXP0<br> E23 DMI_TX[2] PEG_RX#[14] B30<br> 14 DMI_RXP2 PEG_RXN0 PEG_RXP1<br> G23 DMI_TX[3] PEG_RX#[15] A31<br> 14 DMI_RXP3 PEG_RXP2<br> J35 PEG_RXP15 PEG_RXP3<br> PEG_RX[0] PEG_RXP14 PEG_RXP4<br> PEG_RX[1] H34<br> H33 PEG_RXP13 PEG_RXP5<br> 14 FDI_TXN[7:0] FDI_TXN0 PEG_RX[2] PEG_RXP12 PEG_RXP6<br> E22 FDI_TX#[0] PEG_RX[3] F35<br> FDI_TXN1 D21 G33 PEG_RXP11 PEG_RXP7<br> FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_RXP10 PEG_RXP8<br> D19 FDI_TX#[2] PEG_RX[5] E34<br> FDI_TXN3 D18 F32 PEG_RXP9 PEG_RXP9<br> FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_RXP8 PEG_RXP10<br> G21 FDI_TX#[4] PEG_RX[7] D34<br> FDI_TXN5 E19 F33 PEG_RXP7 PEG_RXP11<br> FDI_TXN6 FDI_TX#[5] PEG_RX[8] PEG_RXP6 PEG_RXP12<br> F21 FDI_TX#[6] PEG_RX[9] B33<br><br><br><br><br> PCI EXPRESS -- GRAPHICS<br> FDI_TXN7<br><br><br><br><br> Intel(R) FDI<br> G18 D31 PEG_RXP5 PEG_RXP13<br> FDI_TX#[7] PEG_RX[10] PEG_RXP4 PEG_RXP14<br> PEG_RX[11] A32<br> C30 PEG_RXP3 PEG_RXP15<br> 14 FDI_TXP[7:0] FDI_TXP0 PEG_RX[12] PEG_RXP2<br> D22 FDI_TX[0] PEG_RX[13] A28<br> FDI_TXP1 C21 B29 PEG_RXP1<br> FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_RXP0<br> D20 FDI_TX[2] PEG_RX[15] A30 lane reversal<br> FDI_TXP3 C18 FDI_TX[3] PEG_TXN[15:0] 41<br> FDI_TXP4 G22 L33 C1 0.1uF/16V,X7R DGPU PEG_TXN15 PEG_TXN0<br> FDI_TXP5 FDI_TX[4] PEG_TX#[0] C2 0.1uF/16V,X7R DGPU PEG_TXN14 PEG_TXN1<br> E20 FDI_TX[5] PEG_TX#[1] M35<br> FDI_TXP6 F20 M33 C3 0.1uF/16V,X7R DGPU PEG_TXN13 PEG_TXN2<br> FDI_TXP7 FDI_TX[6] PEG_TX#[2] C4 0.1uF/16V,X7R DGPU PEG_TXN12 PEG_TXN3<br> G19 FDI_TX[7] PEG_TX#[3] M30<br> L31 C5 0.1uF/16V,X7R DGPU PEG_TXN11 PEG_TXN4<br> PEG_TX#[4] C6 0.1uF/16V,X7R DGPU PEG_TXN10 PEG_TXN5<br> 14 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32<br> E17 M29 C7 0.1uF/16V,X7R DGPU PEG_TXN9 PEG_TXN6<br> 14 FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]<br> J31 C8 0.1uF/16V,X7R DGPU PEG_TXN8 PEG_TXN7<br> PEG_TX#[7] C9 0.1uF/16V,X7R DGPU PEG_TXN7 PEG_TXN8<br> 14 FDI_INT C17 FDI_INT PEG_TX#[8] K29<br> H30 C10 0.1uF/16V,X7R DGPU PEG_TXN6 PEG_TXN9<br> PEG_TX#[9] C11 0.1uF/16V,X7R DGPU PEG_TXN5 PEG_TXN10<br> 14 FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29<br> D17 F29 C12 0.1uF/16V,X7R DGPU PEG_TXN4 PEG_TXN11<br> 14 FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11]<br> E28 C13 0.1uF/16V,X7R DGPU PEG_TXN3 PEG_TXN12<br> PEG_TX#[12] C14 0.1uF/16V,X7R DGPU PEG_TXN2 PEG_TXN13<br> PEG_TX#[13] D29<br> D27 C15 0.1uF/16V,X7R DGPU PEG_TXN1 PEG_TXN14<br> PEG_TX#[14] C16 0.1uF/16V,X7R DGPU PEG_TXN0 PEG_TXN15<br> PEG_TX#[15] C26<br> PEG_TXP[15:0] 41<br> L34 C17 0.1uF/16V,X7R DGPU PEG_TXP15 PEG_TXP0<br> PEG_TX[0] C18 0.1uF/16V,X7R DGPU PEG_TXP14 PEG_TXP1<br> PEG_TX[1] M34<br> M32 C19 0.1uF/16V,X7R DGPU PEG_TXP13 PEG_TXP2<br> PEG_TX[2] C20 0.1uF/16V,X7R DG<br/><br/><br/>
<!-- Ezoic - Search Break Responsive - top_of_page -->
<div id="ezoic-pub-ad-placeholder-110">
<script async src="https://pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script>
<!-- Preview Manual Leaderboard Responsive -->
<ins class="adsbygoogle"
style="display:block"
data-ad-client="ca-pub-2156279550025329"
data-ad-slot="6566435862"
data-ad-format="auto"
data-full-width-responsive="true"></ins>
<script>
(adsbygoogle = window.adsbygoogle || []).push({});
</script>
</div>
<!-- End Ezoic - Search Break Responsive - top_of_page -->
<!-- Global site tag (gtag.js) - Google Analytics -->
<script async src="https://www.googletagmanager.com/gtag/js?id=UA-2001630-7"></script>
<script>
window.dataLayer = window.dataLayer || [];
function gtag(){dataLayer.push(arguments);}
gtag('js', new Date());
gtag('config', 'UA-2001630-7');
</script>
</body>
</html>