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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4024B MSI 7-stage binary counter
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

7-stage binary counter
DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop.

HEF4024B MSI

Fig.1 Functional diagram.

PINNING CP MR O0 to O6 clock input (HIGH to LOW triggered) master reset input buffered parallel outputs

APPLICATION INFORMATION Some examples of applications for the HEF4024B are: · Frequency dividers · Time delay circuits Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4024BP(N): HEF4024BD(F): HEF4024BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America

January 1995

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7-stage binary counter HEF4024B MSI

Philips Semiconductors

Product specification

7-stage binary counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns; see also waveforms Fig.4 VDD V Propagation delays CP O0 HIGH to LOW 5 10 15 5 LOW to HIGH On On + 1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH Minimum clock pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWCPH 60 30 20 80 35 25 20 15 15 5 13 18 tTLH tTHL tPHL tPLH tPHL tPLH tPHL 100 40 25 105 45 30 60 25 20 50 20 15 120 45 30 60 30 20 60 30 20 30 15 10 40 20 15 10 5 5 10 25 35 200 75 50 210 85 60 120 50 40 100 40 30 240 90 60 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 73 ns + 29 ns + 17 ns + 78 ns + 34 ns + 22 ns + 33 ns + 14 ns + 12 ns + 23 ns + 9 ns + 7 ns + 93 ns + 34 ns + 22 ns + 10 ns + 9 ns + 6 ns + 10 ns + 9 ns + 6 ns + SYMBOL MIN. TYP. MAX.

HEF4024B MSI

TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL

January 1995

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Philips Semiconductors

Product specification

7-stage binary counter

HEF4024B MSI

VDD V Dynamic power dissipation per package (P) 5 10 15

TYPICAL FORMULA FOR P (µW) 500 fi + (foCL) × VDD2 2100 fi + (foCL) × VDD 5200 fi + (foCL) × VDD
2 2

where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)

Fig.4

Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths and recovery time for MR.

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