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A B C D E
CPU DC/DC
Hawke Intel Discrete Block Diagram ISL6262A 40
INPUTS OUTPUTS
DCBATOUT VCC_CORE
Project code : 91.4W1001.001
CLK GEN SYSTEM DC/DC
1
ICS9LPRS365
Intel Mobile CPU PCB P/N : 48.4W101.0SA TPS5117 42, 43
1
4
Merom 4M Revision : 07212-SA INPUTS OUTPUTS
FSB:667 or 800 MHz 1D05V_S0
5, 6, 7 DCBATOUT
VRAM VRAM 1D8V_S3
16Mbx32x2 51 16Mbx32x2 52
VGA DC/DC SYSTEM DC/DC
Host BUS TPS5117 53 TPS51120 39
CRT 17
RGB CRT
GDDRIII GDDRIII 533/667MHz
700MHz 700MHz INPUTS OUTPUTS INPUTS OUTPUTS
5V_AUX_S5
DDRII DCBATOUT VCC_GFX_CORE_S0 3D3V_AUX_S5
LCD LVDS Slot 0 DCBATOUT 5V_S5
18
NVidia NB8P
Crestline-PM DDRII 667 Channel A 533/667 3D3V_S5
14
(256MB) AGTL+ CPU I/F SYSTEM DC/DC
PCIe x 16
OR DDR Memory I/F DDRII TPS51100 44
HDMI 16 HDMI Slot 1
NVidia NB8M EXTERNAL GRAHPICS
8, 9, 10, 11, 12, 13
DDR II 667 Channel B 533/667 15
INPUTS OUTPUTS
2
(128MB) 2
47, 48, 49, 50 1D8V_S3 0D9V_S3
S-Video SVIDEO Power SW
DMI I/F 27 SYSTEM DC/DC
TI TPS2231
100MHz LDO 44
INPUTS OUTPUTS
1394 25
1394 PCIE x 1 & USB 2.0 x 1 New Card 3D3V_S0 2D5V
Ricoh PCI
INTEL 27
1D8V_S3 1D5V_S0
R5C833 1D8V_S3 1D25V_S0
SD/SDIO/MMC 10/100 NIC
MS/MS Pro/XD
25
CardReader
24, 25
ICH8-M PCIE x 1
Marvell 88E8039 26 RJ45 CONN 27
BATTERY CHARGER
10 USB 2.0/1.1 ports
MAX8731A 38
PCIE PCIE x 1 & USB 2.0 x 1 Mini-Card x 1
28 INPUTS OUTPUTS
6 PCI Express ports 802.11a/b/g
High Definition Audio Mini-Card x 2 29 AD+
PCIE x 2 & USB 2.0 x 2 DCBATOUT
HEADPHONE ATA 66/100 WWAN&BT&Robson BAT+
AZALIA
HP2 SATA
3
AMP 3
MAX4411 ACPI 1.1 USB 2.0 USB 2.0 x 1 CAMERA
32 18 PCB LAYER
LPC I/F
PCI/PCI BRIDGE LPC Bus Lift Side: USB x 2 L1:TOP
23
19, 20, 21, 22 USB 2.0 x 3
L2:GND
MIC IN Azalia Right Side:USB x 1 34
SPI L3:Signal
CODEC KBC
Digital Mic Array Sigmatel Winbond WPC8763L L4:Signal
SATA
PATA
33
STAC 922831 L5:VCC
HP1 L6:Singal
L7:GND
Thermal
Capacity Touch Int. S/W Flash ROM L8:BOT
HDD ODD & Fan
4 2CH OP AMP 23 23 Button30 Pad 36 KB36 CIR 30 1MB 30 4
SPEAKER G792 35
MAX9789A 32
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
System Block Diagram
Size Document Number Rev
A3
Hawke-Intel SA
Date: Saturday, April 21, 2007 Sheet 1 of 55
A B C D E
A B C D E
TI TPS51120
CPU_CORE 3D3V/5V
ISL6262A
Input Signal Output Signal
VID Setting Output Signal
VID0
VID0(I / 3.3V) VRPWRGD
VROK() FOR
1 VID1 51120_EN2 3.3V
1D5V_S0 1
VID1(I / 3.3V) Pull High (3D3V)
PGOUT(OD / 5V)
VID2 51120_EN1 FOR 3D3V_S0 2D5V_S0
VID2(I / 3.3V) 5.0V INPUT OUT
VID3
VID3(I / 3.3V)
Output Power APL5912
VID4
VID4(I / 3.3V) VCC_CORE_S0(Imax=35A)
VCC_CORE_PWR(O)
VID5 DCBATOUT_51120
VID5(I / 3.3V) VIN
2D5V_S0
5V_AUX_S5
Input Signal
Input Power Output Power 3D3V_S0 2D5V_S0
VCORE_EN INPUT OUT
EN (I / 3.3V)
3D3V_AUX_S5
DCBATOUT_51120 G9131
Voltage Sense VIN
5V_S5 (5.4A)
COREFB 5V(O)
VSEN(I / Vcore)
REG5V_IN(I / 5V) 1D2V_S0
2 2
COREFB#
RGND(I / Vcore) 3D3V_S5 (4A)
3D3V(O) 3D3V_S5 1D2V_S0
INPUT OUT
Input Power
DCBATOUT APL5332KAC-TRLGP
VCC(I)
5V_S0
VCC(I)
Adapter
3D3V_S0
VCC(I) Input Signal Output Signal Charger_ISL6255
AD_IN
AD_OFF (I) (O)
Input Signal Output Signal
CHARGE_OFF AD_IN
CLS (I / 3.3V) LDO (O / 5.4V)
Input Power Output Power
BT_TH
AD_JK AD+ THM (I / 3.3V) CHARGE_LED#
VCC(I) VCC(O) XTAL2/PB4 (O/5V)
BAT+SENSE
3
5V_AUX_S5 BATT (I / 3.3V) 3
VCC(I) XTAL1/PB3 (O/5V) BL2#
TI TPS51100 BT_SCL_5
SCL (IO / 5V)
0.9V/DDR_VREF_S3 BT_SDA_5
SDA (IO / 5V)
ISL6268_1D8V Output Power
Input Signal FLASH_GPIO1 DCBATOUT
RESET#/PB5 (I/5V) VCC (O)
PM_SLP_S5# S5
FLASH_GPIO2
S3 Input Signal Output Power PB0/MOSI/AIN0 BT+
1D8V_S3_EN FOR VCC (O)
SS_STBY1(I / 5V) 1.2V AC_IN
PB0/MOSI/AIN0
Output Power
1D8V_S3
1D8V_PWR
0D9V_DDR_VTT 5V_S5 Input Power Input Power
VCC(O) VCC AD+
Input Power DCIN (I)
DCBATOUT
VIN
DCBATOUT DDR_VREF_S3
VCC(I) VCC(O) ISL6268_1D05V
5V_S5
4 VCC(I) 4
Input Signal Output Power
1D05V_EN FOR
SS_STBY1(I / 5V) 1.2V Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1D05V_S0 (15A) Taipei Hsien 221, Taiwan, R.O.C.
1D05V_PWR Title
5V_S5 Input Power
VCC Power Block Diagram
DCBATOUT Size Document Number Rev
A3
VIN Hawke-Intel SA
Date: Saturday, April 21, 2007 Sheet 2 of 55
A B C D E
A B C D E
INTEL ICH8-M STRAP PIN 20,22,34 +RTCVCC +RTCVCC
5,6,7,8,10,11,12,20,22,42,46 1D05V_S0 1D05V_S0
8,11,22,44,47,48,49 1D25V_S0 1D25V_S0
Signal Usage/When Sampled Comment XOR Chain Entrance Strap 26 1D2V_LAN_S5 1D2V_LAN_S5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 ICH_RSVD
tp3 AZ_DOUT_ICH Description
27 1D5V_NEW_S0 1D5V_NEW_S0
1 PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD 1
0 1 Enter XOR Chain
Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of 6,11,20,21,22,27,28,29,44 1D5V_S0 1D5V_S0
1 0 Normal Operation(default)
RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1
8,11,12,14,15,43,44,45,46 1D8V_S3 1D8V_S3
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. 26,27 2D5V_LAN_S5 2D5V_LAN_S5
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
30,33,34,35,38,39,46 3D3V_AUX_S5 3D3V_AUX_S5
GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should 26,27 3D3V_LAN_S5 3D3V_LAN_S5
not be pull HIGH.
4,8,11,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,40,42,44,45,46,47,49,50,53 3D3V_S0 3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space). 19,21,22,26,27,28,29,30,37,39,45,46 3D3V_S5 3D3V_S5
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable
Top-Swap bit until the system is rebooted high = default 33,38,39,46 5V_AUX_S5 5V_AUX_S5
without GNT3# being pulled down. BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit 16,17,18,21,22,23,30,32,34,35,36,40,44,45,46 5V_S0 5V_S0
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI 22,23,28,29,30,34,36,37,39,42,43,44,45,53 5V_S5 5V_S5
1 1 LPC(Default)
Integrated VccSus1_05 37,38,46 AD+ AD+
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high 18,38,39,40,41,42,43,45,46,53 DCBATOUT DCBATOUT
SM_INTVRMEN High=Enable Low=Disable
2 sampled. 2
14,15,44,46 DDR_VREF_S0 DDR_VREF_S0
integrated VccLan1_05VccCL1_05
Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM 8,14,15,44 DDR_VREF_S3 DDR_VREF_S3
LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable
/Disable. Always sampled.
18 +LCDVDD +LCDVDD
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8) 6,7,41 VCC_CORE_S0 VCC_CORE_S0
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot
TP3 XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing. INTEL ICH8-M INTEGRATED
Internal Pull-Up.If sampled low,the Flash Descriptor
GPIO33/
HDA_DOCK_EN#
Flash Descriptor Security Security will be overidden.if high,the Security
Override Strap measures defined in the Flash Descriptor will be in
PULL-UPS and PULL-DOWNS
Rising Edge of PWROK. effect.
8.2K PULL HIGH
This should only be used in manufacturing SIGNAL Resistor Type/Value
environments HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
3 3
HDA_SDIN[3:0] PULL-DOWN 20K
HDA_SDOUT PULL-DOWN 20K
HDA_SYNC PULL-DOWN 20K
GNT[3:0] PULL-UP 20K
INTEL CRESTLINE STRAP PIN GPIO[20] PULL-DOWN 20K
CFG Strap LOW 0 HIGH 1 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
CFG 5 LAN_RXD[2:0] PULL-UP 20K
DMI X 2 DMI X 4
CFG 8 LDRQ[0] PULL-UP 20K
Low Power PCI Express Normal Low Power mode
CFG 9 LDRQ[1]/GPIO23 PULL-UP 20K
PCI Express Graphics Lane Reversal Normal Mode(Lanes
Lane Reversal number in order) PME# PULL-UP 20K
CFG 16
FSB Dynamic ODT Disabled Enabled PWRBTN# PULL-UP 20K
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane SATALED# PULL-UP 20K
CFG 20 Only PCIE or SDVO PCIE and SDVO are
Concurrent SDVO/PCIE is operation operation simultaneous SPI_CS1# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present SPI_CLK PULL-UP 20K
Present
SDVO Present SPI_MOSI PULL-UP 20K
4 4
CFG 12 XOR/ALL-Z SPI_MISO PULL-UP 20K
CFG 13 Wistron Corporation
LL(00) Reserved TACH_[3:0] PULL-UP 20K
LH(01) XOR Mode Enabled 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
HL(10) All Z Mode Enabled SPKR PULL-DOWN 20K Taipei Hsien 221, Taiwan, R.O.C.
HH(11) Normal Operation
TP[3] PULL-UP 20K Title
USB[9:0][P,N] PULL-DOWN 15K Table of Content
Size Document Number Rev
A3
CL_RST# TBD Hawke-Intel SA
Date: Saturday, April 21, 2007 Sheet 3 of 55
A B C D E
3D3V_S0 A 3D3V_S0_CK505 B C D E
L102
1 2 3D3V_S0_CK505 3D3V_S0_CK505_IO
0R3-0-U-GP
1
1
1
1
1
1
1
C1552 C1553 C1555 C1556 C1557 C1558 C1559
SC1U10V3KX-3GP
SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
X1
CLK_XTAL_IN 1 2 CLK_XTAL_OUT
X-14D31818M-36GP
1
1
1 C1560 C1561
1
SC27P50V2JN-2-GP SC27P50V2JN-2-GP