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PIRQ# REQ#/GNT# IDSEL
DC/DC BATT SELECTOR
TPC01 BLOCK DIAGRAM VGA
CARDBUS
IEEE 1394
X
C, (B)
B
X
3
2
X
22
23
PG 37 MINI-PCI E, F 1 20
1.25VDDR
2.5VDDR LAN D 0 18
BATT CHARGER USB 2.0 X X X
A AC/BATT A
PG 33 CONNECTOR PG 36 CLOCKS
1.5V/1.8V Celeron/Celeron-M ICS950810
PG 32 CPU CORE
System Power
MAX1907 PG 34 PG 12
MAX1632 (Micro-FCPGA)
PG 35 Discharge I/O BOARD
PG 3,4 50 Pins
CKTS
PG 38 LVDS LVDS Connector LINEOUT
PG 28 MIC JACK
400MHZ USB 2.0 X2
RJ11
CH7011 TV-OUT
PG 26
Montara-GM
DDR-SODIMM1
266/200 MHZ DDR MGM CRT&S-VIDEO
PG 10
PG 27
B
732 Micro-FCBGA B
PG 5,6,7
DDR-Termiation
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PG 11 66(266)MHZ, 1.8V
HUB 1.5 I/F
33MHZ, 3.3V PCI
Primary IDE ATA 66/100 ICH4-M
HDD PG 22 421 BGA MINI-PCI CARDBUS 1394 LAN
SOCKET CB1410 VT6307
Secondary IDE PG 8,9 PG 21 PG 17 PG 19 PG 20
DVD ROM
PG 22 CARDBUS
RJ45
SLOT
C PG 18 PG 25 C
USB connec*2
USB 2.0
AC LINK
PG 29 3.3V LPC, 33MHz USB 1.1
AC LINK
SIO ITE8705 PC87591
HEAD PHONE
100 Pins TQFP 176 Pins LQFP AUDIO AUDIO
LINE IN
CODEC AMP
LM4869 EXT. /INT.
PG 26 PG 27 PG15 MIC
PG 14
PG 15,16
LPT LED/B Touchpad Keyboard FLASH FAN 1,2
D PG 24 PG 31 PG 31 PG 31 PG 13 PG 30 D
TECHNOLOGY COPR.
Title
Block Diagram
Document Number R ev
TPC01 A
Date: Thursday, February 12, 2004 Sheet 1 of 39
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3V_S5
=3VAL Device
S5_ON
Rails CPU GMCH ICH4-MPC87591 DDR AUDIO HDD LCD INV USB2.0 LAN
3V_591
VA +3V
VIN =3VPCU MAINON 5VPCU
CHARGER MAX1632 @4A
SELECTOR 5V_S5 3V_591
S5_ON
C C
3V_S5
VBAT 5VPCU +5V
MAINON
@4A 5V_S5
5VSUS
SUSON 1.5V_S5
12VOUT +12V
5VSUS
+1.8V
SC1565 2.5VSUS
SMDDR
SC1486 2.5VSUS +2.5V _VTERM
MAINON
@7A
5VSUS +5V
EN @3A SMDDR_VTERM
+3V
+2.5V
+1.5V
1.5V_S5 +1.5V
B MAX1844 MAINON 1.2VCCT B
@4A
S5_ON
EN +1.8V
VCC_CORE
VCC_CORE
MAX1907 VCCP
@25A
+12V
VRON
EN
S0 POWER => ICH4 3.3*165 +67.5*1.5
=> ICH4 LAN LOGIC =3.3*9.2+1.5*15.5 700MW
1.5V_S5 VCCP
SMB DIAGRAM
SC338
5VSUS
VIN DRV1
ICH4-M CK408
VRON DRV2 DDR
1.5V_S5 1.2VCCT
A A
SSC
HWPG
HWPG_POWER_G
GMCH
HWPG_POWER PGD PC87591E MAX6648
IMVPOK
CKTS
ICH4 CPU
TECHNOLOGY COPR.
Title
BATTERY
Power Diagram
87591
Document Number R ev
TPC01 A
Date: Thursday, February 12, 2004 Sheet 2 of 39
3 2 1
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HD#[0..63] +3V +5V R1 R0603 +/-1% 150
U1A HD#[0..63] 5 +3V C1
5 HA#[3..31]
HA#[3..31]
HA#3 P4 A3# D0# A19 HD#0 R2 * 0.1uF
16V, X7R, +/-10%
HA#4 HD#1 10K Q1 C0603
U4
Banias A25
G
HA#5 A4# D1# HD#2 +/-5% 2N7002
V3 A5# D2# A22
HA#6 R3 B21 HD#3 R0603
HA#7 A6# D3# HD#4 THDAT_SMB U2
V2 A7# D4# A24 S DMBDATA MBDATA 13,31
A
HA#8
HA#9
W1
T4
A8# 1 OF 3 D5# B26
A21
HD#5
HD#6
THCLK_SMB 8 SMCLK VCC 1
THERMDA A
HA#10 A9# D6# HD#7 THDAT_SMB C2
W2 A10# D7# B20 7 SMDATA DXP 2
HA#11
HA#12
Y4
Y1
A11#
A12#
D8#
D9#
C20
B24
HD#8
HD#9
+3V +5V
T1 1 6 -ALT DXN 3
* 2.2nF
50V, X7R, +/-20%
HA#13 U1 D24 HD#10 C0603
HA#14 A13# D10# HD#11 R3 THERMDC
AA3 A14# D11# E24 5 GND -OVT 4
HA#15 Y3 C26 HD#12 10K Q2
G
A15# D12#
HA#16 AA2 A16# D13# B23 HD#13 +/-5% 2N7002 For ATE MAX6648
HA#17 AF4 E23 HD#14 R0603 R4 R0603 1K +3V
HA#18 A17# D14# HD#15 THCLK_SMB
AC4 A18# D15# C25 S D MBCLK MBCLK 13,37
+/-5%
HA#19 AC7 H23 HD#16
A19# D16# 6648_OVT# 30
HA#20 AC3 G25 HD#17
HA#21 A20# D17# HD#18
AD3 A21# D18# L23
HA#22 AE4 M26 HD#19
HA#23 A22# D19# HD#20
AD2 A23# D20# H24
HA#24 AB4 F25 HD#21
HA#25 A24# REQUEST DATA D21# HD#22
AC6 A25# D22# G24
HA#26 AD5 PHASE PHASE J23 HD#23
HA#27 A26# D23# HD#24
AE2 SIGNALS SIGNALS M23
HA#28 A27# D24# HD#25
AD6 A28# D25# J25
HA#29 AF3 L26 HD#26
HA#30 A29# D26# HD#27
AE1 A30# D27# N24
HA#31 AF1 M25 HD#28 +3V +3V
A31# D28# HD#29 VCCP-PM
D29# H26
N25 HD#30
D30# HD#31
D31# K25
U3 Y26 HD#32 R5 R6
5 HADSTB0# ADSTB0# D32#
AE5 AA24 HD#33 2K 330
5 HADSTB1# ADSTB1# D33#
T25 HD#34 IERR# R7 R0603 +/-5% 56 +/-1% +/-5%
D34# HD#35 CPUPWRGD R8 R0603 +/-5% 330 R0603 R0603
D35# U23
R2 V23 HD#36 VCCP-PM Dummy ICH_THRM#
5 HREQ#0 REQ0# D36# ICH_THRM# 9,13,30
D
B P3 R24 HD#37 TCK R9 R0603 +/-1% 27.4 B
5 HREQ#1 REQ1# D37#
T2 R26 HD#38 TRST# R10 R0603 +/-5% 680 Q3
5 HREQ#2 REQ2# D38#
P1 R23 HD#39 R11 2N7002
5 HREQ#3 REQ3# D39#
T1 AA23 HD#40 56 G
5 HREQ#4 REQ4# D40#
U26 HD#41 +/-1% Dummy
D41# HD#42 R0603
D42# V24
C
S
ERROR HD#43
5 ADS# N2 ADS# SIGNALS D43#
D44#
U25
V26 HD#44 R516 should CPU_PROCHOT# R12 330 B Q4
MMBT3904
Y23 HD#45 R0603 +/-5%
D45#
D46# AA26 HD#46 be place Dummy Dummy
E
IERR# A4 Y25 HD#47
IERR# D47#
5 HBREQ0# N4
D48# AB25
AC23
HD#48
HD#49 within 2" of
BREQ0# D49#
5
5
BPRI#
BNR#
J3
L1
BPRI#
BNR#
ARBITRATION
PHASE D50#
D51#
AB24
AC20
HD#50
HD#51 the processor ;
J2 SIGNALS AC22 HD#52
5 HLOCK#
K3
LOCK# D52#
D53# AC25
AD23
HD#53
HD#54
others place
5 HIT#
5 HITM# K4
L4
HIT#
HITM#
SNOOP PHASE
SIGNALS
D54#
D55# AE22
AF23
HD#55
HD#56
near ITP
5 DEFER# DEFER# D56#
AD24 HD#57
BPM0# D57# HD#58
C8 BPM0# D58# AF20
BPM1# B8 RESPONSE AE21 HD#59
BPM2# BPM1# PHASE D59# HD#60
A9 BPM2# D60# AD21
BPM3# C9 SIGNALS AF25 HD#61
BPM3# D61# HD#62 VCCP-PM VCCP-PM
5 HTRDY# M3 TRDY# D62# AF22
H1 AF26 HD#63 +3V
5 RS#0 RS0# D63#
5 RS#1 K1 RS1#
5 RS#2 L2 RS2# R13 R14 R15 R16
A20M# C2 C23 54.9 54.9 39.2 150 R17
C 8 A20M# A20M# DSTBN0# HDSTBN0# 5 C
FERR# D3 PC C22 +/-1% +/-1% +/-1% +/-5% 150
8 FERR# FERR# DSTBP0# HDSTBP0# 5
IGNNE# A3 COMPATIBILITY K24 R0603 R0603 R0603 R0603 +/-5%
8 IGNNE# IGNNE# DSTBN1# HDSTBN1# 5
R18 +/-5% R0603 0 R_CPUPWRGD E4 SIGNALS L24 dummy R0603
9 CPUPWRGD PWRGOOD DSTBP1# HDSTBP1# 5
SMI# B4 W25
8 SMI# SMI# DSTBN2# HDSTBN2# 5
DSTBP2# W24 HDSTBP2# 5
TCK A13 AE24 TDI DBR#
TCK DSTBN3# HDSTBN3# 5
TDO A12 DIAGNOSTIC AE25 TMS
TDO DSTBP3# HDSTBP3# 5
TDI C12 & TEST
TMS TDI
C11 SIGNALS
TRST# TMS BPM0# T2
B13 TRST# DBI0# D25 HDBI0# 5 1
T3 1 A16 J26
ITP_CLK0 DBI1# HDBI1# 5
T4 1 A15 T24 TDO BPM1# 1 T5
ITP_CLK1 DBI2# HDBI2# 5
PREQ# B10 AD20
PREQ# DBI3# HDBI3# 5
P RDY# A10 BPM2# 1 T6
DBR# PRDY#
9 DBR# A7 DBR# DBSY# M2 DBSY# 5
H2 CPURST# BPM3# 1 T7
DRDY# DRDY# 5
8 INTR D1 LINT0
D4 EXECUTION P RDY# 1 T8
8 NMI LINT1
STPCLK# C6 CONTROL B14
8 STPCLK# STPCLK# BCLK1 HCLK_CPU# 12
CPUSLP# A6 SIGNALS B15 PREQ# 1 T9
8 CPUSLP# SLP# BCLK0 HCLK_CPU 12
DPSLP# B7
6,8 DPSLP# DPSLP#
Del ITP700
THERMDA B18 B5 CPUINIT#
CPUINIT# 8 Del R434,R439,C542,R442
THERMDC THERMDA INIT#
A18 THERMDC
B11 R_CPURST# R19 +/-5% R0603 0
RESET# CPURST# 5
THERMTRIP# C17
9 THERMTRIP# THERMTRIP# THERMAL DIODE C19
DPWR# DPWR# 6
CPU_PROCHOT# B17
PROCHOT#
A1
D D
Banias Processor
A1
www.hocnghetructuyen.vn TECHNOLOGY COPR.
Title
Banias Host
Document Number R ev
TPC01 A
Date: Thursday, February 12, 2004 Sheet 3 of 39
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