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5 4 3 2 1
ZRI/ZQI Block Diagram
PCB STACK UP
D VRAM P22, 23 LAYER 1 : TOP D
Channel A LAYER 2 : GND
DDRIII-SODIMM Channel A(1600 MHZ)
APU PEG0~8(PCI-E x 8) GPU
DDR GFX LAYER 3 : IN1
P12 Mars XT(25W) Channel B
LAYER 4 : IN2
DRAM 29mm X 29mm
Richland APU VRAM DDR3-128MB*8 = 1GB LAYER 5 : SVCC
DP2 eDP PANEL P14~21
(35W) P25 VRAM DDR3-256MB*8 = 2GB
X'TAL LAYER 6 : IN3
Channel B 27.0MHz
27mm X 31mm LAYER 6 : GND
DP1 HDMI CONN
FP2 827pin BGA P26 LAYER 8 : BOT
P13,14
256Mb*16*8pcs/8 = 4GB
P3, 4, 5, 6 TXP/N,0/1
DP0
UMI
TXP/N,2/3 TXP/N,2/3
USB3-1 SW USB3 MINI DP CONN
UMI LINK USB2-11
HD3SS2521 USB2
2.5GT /s
P25 P25
C C
UMI(x4)
SATA0
SATA - HDD USB3-0
P31 USB3.0 USB3.0 Con.
USB2-10
SATA (charger) P34
SATA1
SATA - SSD
P31
USB2-7
USB Con. USB2-0 MINI CARD
P33
PCIE-0 WLAN+BT
FCH P30
Charger (BQ24737RGRR)
PCIE
D/B USB2-3
USB Con. P38
LAN & CR RJ45 Conn.
P33
USB2.0
Bolton M3 PCIE-1 QCA8175 P28 SYSTEM 5V/3V (TPS51225RUKR)
USB2-6 24.5mm X 24.5mm 10/100/1G P39
CCD Card Reader Conn.
P26 P28 +1.5VSUS(TPS51216)
X'TAL P29
B P8 B
RTC 25MHz
P40
X'TAL
USB2-8 25MHz
Touch Panel
+1.2V(TPS51211) / +2.5V
P26 BATTERY X'TAL
P8 32.768KHz P8 P41
1.1V_DUAL(TPS51211)
P7, 8, 9, 10, 11
P42
HDAUDIO
SPIROM
BIOSROM
LPC P9
+VDD_CORE (ISL62771)
P43
+VGPU_CORE(TPS51728)
P44
+PCIE_VDDC_GFX(TPS51211)
Audio Codec
EC 985L P45
ALC3225 P32 P37 +1.8V_GFX(TPS54318RTER)
P46
A A
Discharge /Thermal
INT. MIC HP/MIC AMP APU FAN GPU FAN HALL Sensor K/B Touch Pad TPM Conn.
P47
P32 P32 ALC1001 P35 P35 P33 P35 P35 P31
P32
D/B
Quanta Computer Inc.
Seaker Conn. PROJECT :ZRI/ZQI
P32 Size Document Number Rev
BLOCK DIAGRAM A1A
Date: Wednesday, April 24, 2013 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
BOM Option
Power Sequence
ITEM DESCRIPTION MARK
1 LVDS Panel Sku LVDS@
AC IN
Hudson M3
2
3V/5VPCU SMBUS
eDP Panel Sku eDP@
FCH SMBUS Pin NO. SMBUS Function Define
3 VGA Sku EV@ NBSWON#
D
PCLK_SMB AD26 D
4 VGA Thames Sku EV_T@ DDR / WLAN
DNBSWON# PDAT_SMB AD25
5 VGA Mars Sku EV_M@ (+3V)
S5_ON/S5
VGA Sku for Thames and Mars stuff SCLK1 T7
6 different value parts EV_SP@ Touch Pad
SDATA1 R7
RSMRST#
(+3V_S5)
7 GPU 128bit Sku EV_128@
SMB_EC_CLK (SCLK2) H19
GPU 128bit Sku of Special part PCIE_WAKE# EC
8 value change EV_128SP@ SMB_EC_DAT (SDATA2) G19
(+3V_S5)
SUSC
9 USB Charge Functions Sku CH@
SCLK3 G22
Not used
10 No USB Charge Functions Sku NCH@ SUSB SDATA3 G21
(+3VPCU)
11 USB3.0 Re-Driver Sku RD@
SUSON
SCL4 J19
12 No USB3.0 Re-Driver Sku NRD@ Not used
SDATA4 K19
MAINON
13 Always connect functions Sku AC@ (+3V_S5)
14 No Always connect functions Sku NAC@ VR_ON
C C
Special part value change or modify
15 for different BOM sku SP@ CPU_CORE
EC
16 Key Board Back light Sku KBL@ VRM_PWRGD
SMBUS
KBC SMBUS Pin NO. SMBUS Function Define
17 SSD Sku SSD@
HWPG
18 Touch panel Sku TP@ MBCLK 70
ECPWROK MBDATA 69 Battery, FCH
(+3VPCU)
Page 9 GPIO strap pin SB_PWRGD_IN
APU_SIC_EC 67
ITEM DESCRIPTION MARK CPU RESET APU_SID_EC 68 APU
(+3V_S5)
1 Synaptics touch pad SYNP@ CPU POWER OK
GPUT_CLK 119
2 ELAN touch pad ELAN@
GPUT_DATA 120 GPU
3 For UMA Sku UMA@ (+3V_GFX)
B 4 ELPIDA on board DRAM ELP@ B
TPCLK 72
5 HYNIX on board DRAM HYN@ TPDATA 71 Touch Pad
(+3V)
EC FCH Device I2C_Device(S)
I2Ce_1(M) I2Cf_2(M) Charger Battery ALL/S5
I2Ce_2(M) APU ALL
I2Ce_3(M)
I2Cf_3(M) APU S5
I2Cf_1(M) S5
A
I2Cf_0(M) DDR WLAN/3G Image Sensor S0 A
EC will Conflict with FCH.
Do not mount
Quanta Computer Inc.
PROJECT : ZRI/ZQI
Size Document Number Rev
SYSTEM INFORMATION A1A
Date: Wednesday, April 24, 2013 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
U48A
[15] PEG_RXP0 AP1 AN1 PEG_TXP0_C C695 [email protected]/10V_4 PEG_TXP0 [15]
P_GFX_RXP[0] P_GFX_TXP[0] PEG_TXN0_C C696 [email protected]/10V_4
[15] PEG_RXN0 AP2 P_GFX_RXN[0] P_GFX_TXN[0] AN2 PEG_TXN0 [15]
[15] PEG_RXP1 AM1 AM4 PEG_TXP1_C C693 [email protected]/10V_4 PEG_TXP1 [15]
P_GFX_RXP[1] P_GFX_TXP[1] PEG_TXN1_C C694 [email protected]/10V_4
[15] PEG_RXN1 AM2 P_GFX_RXN[1] P_GFX_TXN[1] AM3 PEG_TXN1 [15]
[15] PEG_RXP2 AK3 AK2 PEG_TXP2_C C692 [email protected]/10V_4 PEG_TXP2 [15]
P_GFX_RXP[2] P_GFX_TXP[2]
PEG X 8
PEG X 8
D AK4 AK1 PEG_TXN2_C C691 [email protected]/10V_4 D
[15] PEG_RXN2 P_GFX_RXN[2] P_GFX_TXN[2] PEG_TXN2 [15]
[15] PEG_RXP3 AJ1 AH1 PEG_TXP3_C C690 [email protected]/10V_4 PEG_TXP3 [15]
P_GFX_RXP[3] P_GFX_TXP[3] PEG_TXN3_C C689 [email protected]/10V_4
[15] PEG_RXN3 AJ2 P_GFX_RXN[3] P_GFX_TXN[3] AH2 PEG_TXN3 [15]
[15] PEG_RXP4 AH4 AF3 PEG_TXP4_C C688 [email protected]/10V_4 PEG_TXP4 [15]
P_GFX_RXP[4] P_GFX_TXP[4] PEG_TXN4_C C687 [email protected]/10V_4
[15] PEG_RXN4 AH3 P_GFX_RXN[4] P_GFX_TXN[4] AF4 PEG_TXN4 [15]
[15] PEG_RXP5 AF2 AE1 PEG_TXP5_C C686 [email protected]/10V_4 PEG_TXP5 [15]
P_GFX_RXP[5] P_GFX_TXP[5] PEG_TXN5_C C685 [email protected]/10V_4
[15] PEG_RXN5 AF1 P_GFX_RXN[5] P_GFX_TXN[5] AE2 PEG_TXN5 [15]
[15] PEG_RXP6 AD1 AD4 PEG_TXP6_C C683 [email protected]/10V_4 PEG_TXP6 [15]
P_GFX_RXP[6] P_GFX_TXP[6] PEG_TXN6_C C684 [email protected]/10V_4
[15] PEG_RXN6 AD2 P_GFX_RXN[6] P_GFX_TXN[6] AD3 PEG_TXN6 [15]
PEG_TXP7_C C681 [email protected]/10V_4
GRAPHICS
[15] PEG_RXP7 AB3 P_GFX_RXP[7] P_GFX_TXP[7] AB2 PEG_TXP7 [15]
[15] PEG_RXN7 AB4 AB1 PEG_TXN7_C C682 [email protected]/10V_4 PEG_TXN7 [15]
P_GFX_RXN[7] P_GFX_TXN[7]
AA1 P_GFX_RXP[8] P_GFX_TXP[8] Y1
FP2 only support PEG X 8 AA2 P_GFX_RXN[8] P_GFX_TXN[8] Y2 FP2 only support PEG X 8
Y4 P_GFX_RXP[9] P_GFX_TXP[9] V3
Y3 P_GFX_RXN[9] P_GFX_TXN[9] V4
V2 P_GFX_RXP[10] P_GFX_TXP[10] U1
V1 U2
T1
P_GFX_RXN[10]
P_GFX_RXP[11]
P_GFX_TXN[10]
P_GFX_TXP[11] T4 A10 AJ05757RT01
T2 P_GFX_RXN[11] P_GFX_TXN[11] T3
P3 P2
P4
P_GFX_RXP[12]
P_GFX_RXN[12]
P_GFX_TXP[12]
P_GFX_TXN[12] P1 A8 AJ05557UT01
N1 P_GFX_RXP[13] P_GFX_TXP[13] M1
N2 M2
M4
P_GFX_RXN[13]
P_GFX_RXP[14]
P_GFX_TXN[13]
P_GFX_TXP[14] K3 A6 AJ053578T01
M3 P_GFX_RXN[14] P_GFX_TXN[14] K4
K2 P_GFX_RXP[15] P_GFX_TXP[15] J1
K1 P_GFX_RXN[15] P_GFX_TXN[15] J2
AH5 P_GPP_RXP[0] P_GPP_TXP[0] AG7
AH6 P_GPP_RXN[0] P_GPP_TXN[0] AG8
C AG5 AE7 C
P_GPP_RXP[1] P_GPP_TXP[1]
AG6 P_GPP_RXN[1] P_GPP_TXN[1] AE8
AE6 P_GPP_RXP[2] P_GPP_TXP[2] AD7
AE5 P_GPP_RXN[2] P_GPP_TXN[2] AD8
AD6 P_GPP_RXP[3] P_GPP_TXP[3] AB6
AD5 AB5
GPP
P_GPP_RXN[3] P_GPP_TXN[3]
[8] UMI_RXP0 AM10 AN6 UMI_TXP0_C C709 0.1u/10V_4 UMI_TXP0 [8]
P_UMI_RXP[0] P_UMI_TXP[0] UMI_TXN0_C C708 0.1u/10V_4
[8] UMI_RXN0 AN10 P_UMI_RXN[0] P_UMI_TXN[0] AM6 UMI_TXN0 [8]
[8] UMI_RXP1 AN8 AP6 UMI_TXP1_C C710 0.1u/10V_4 UMI_TXP1 [8]
P_UMI_RXP[1] P_UMI_TXP[1] UMI_TXN1_C C713 0.1u/10V_4
[8] UMI_RXN1 AM8 P_UMI_RXN[1] P_UMI_TXN[1] AR6 UMI_TXN1 [8]
[8] UMI_RXP2 AP8 AP4 UMI_TXP2_C C705 0.1u/10V_4 UMI_TXP2 [8]
P_UMI_RXP[2] P_UMI_TXP[2] UMI_TXN2_C C707 0.1u/10V_4
[8] UMI_RXN2 AR8 P_UMI_RXN[2] P_UMI_TXN[2] AR4 UMI_TXN2 [8]
[8] UMI_RXP3 AR7 AP3 UMI_TXP3_C C702 0.1u/10V_4 UMI_TXP3 [8]
P_UMI_RXP[3] P_UMI_TXP[3] UMI_TXN3_C C704 0.1u/10V_4
[8] UMI_RXN3 AP7 P_UMI_RXN[3] P_UMI_TXN[3] AR3 UMI_TXN3 [8]
UMI
+1.2V_VDDP R576 196/F_6 P_ZVDDP AR11 AP11 P_ZVSS
P_ZVDDP P_ZVSS
RICHLAND_APU_BGA813
R570
196/F_6
B B
HDT+ Connector for Debug only
+1.5V
R545 R552
+1.5VSUS *1K_4 *1K_4
J1
U44
1 2 APU_TCK 1 6 APU_RST_L_BUF
CPU_VDDIO1 CPU_TCK APU_TCK [5] [5,8] APU_RST# A1 Y1
3 4 APU_TMS
GND1 CPU_TMS APU_TMS [5]
5 6 APU_TDI 2 5 +3V
GND2 CPU_TDI APU_TDI [5] GND VCC
7 8 APU_TDO
GND3 CPU_TDO APU_TDO [5]
APU_TRST# 9 10 APU_PWROK_BUF 3 4 APU_PWROK_BUF
[5] APU_TRST# CPU_TRST_L CPU_PWROK_BUF [5,8] APU_PWRGD_R A2 Y2
R549 *10K_4 11 12 APU_RST_L_BUF
R540 *10K_4 CPU_DBRDY3 CPU_RST_L_BUF
13 CPU_DBRDY2 CPU_DBRDY0 14 APU_DBRDY [5]
R530 *10K_4 15 16 APU_DBREQ# C703 *74LVC2G07
CPU_DBRDY1 CPU_DBREQ_L APU_DBREQ# [5]
17 GND4 CPU_PLLTEST0 18 APU_TEST19_PLLTEST0 [5]
19 20 *0.1u/10V_4
CPU_VDDIO2 CPU_PLLTEST1 APU_TEST18_PLLTEST1 [5]
*HDT+ HEADER
A A
+1.5VSUS
Close by HDT+ Conector
APU_TDI
APU_TCK
R558
R565
1K_4
1K_4
Quanta Computer Inc.
APU_TMS R563 1K_4
APU_TRST# R551 1K_4 PROJECT : ZRI/ZQI
APU_DBREQ# R533 1K_4 Size Document Number Rev
A1A
APU 1/4(PCIE/UMI/GPP/HDT)
Date: Wednesday, April 24, 2013 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
Soldermask openings for all bottom side vias/TPs under FS1
M_B_DQ[0..63] [13,14]
U48B M_A_DQ[0..63] [12] [13,14] M_B_A[15:0] U48C
[12] M_A_A[15:0]
M_A_A0 AA28 F15 M_A_DQ0 M_B_A0 Y33 C16 M_B_DQ0
M_A_A1 MA_ADD[0] MA_DATA[0] M_A_DQ1 M_B_A1 MB_ADD[0] MB_DATA[0] M_B_DQ1
R29 MA_ADD[1] MA_DATA[1] E15 R32 MB_ADD[1] MB_DATA[1] B17
M_A_A2 T30 H19 M_A_DQ2 M_B_A2 T31 B20 M_B_DQ2
M_A_A3 MA_ADD[2] MA_DATA[2] M_A_DQ3 M_B_A3 MB_ADD[2] MB_DATA[2] M_B_DQ3
R28 MA_ADD[3] MA_DATA[3] F19 P33 MB_ADD[3] MB_DATA[3] C20
M_A_A4 R26 E14 M_A_DQ4 M_B_A4 P32 A16 M_B_DQ4
D M_A_A5 MA_ADD[4] MA_DATA[4] M_A_DQ5 M_B_A5 MB_ADD[4] MB_DATA[4] M_B_DQ5 D
P26 MA_ADD[5] MA_DATA[5] H15 P31 MB_ADD[5] MB_DATA[5] B16
M_A_A6 P27 E17 M_A_DQ6 M_B_A6 N32 B19 M_B_DQ6
M_A_A7 MA_ADD[6] MA_DATA[6] M_A_DQ7 M_B_A7 MB_ADD[6] MB_DATA[6] M_B_DQ7
P30 MA_ADD[7] MA_DATA[7] D18 M33 MB_ADD[7] MB_DATA[7] A20
M_A_A8 P29 M_B_A8 M32
M_A_A9 MA_ADD[8] M_A_DQ8 M_B_A9 MB_ADD[8] M_B_DQ8
M28 MA_ADD[9] MA_DATA[8] G20 L32 MB_ADD[9] MB_DATA[8] B22
M_A_A10 AB26 E20 M_A_DQ9 M_B_A10 AB31 C22 M_B_DQ9
M_A_A11 MA_ADD[10] MA_DATA[9] M_A_DQ10 M_B_A11 MB_ADD[10] MB_DATA[9] M_B_DQ10
M26 MA_ADD[11] MA_DATA[10] H23 M31 MB_ADD[11] MB_DATA[10] A26
M_A_A12 M29 G23 M_A_DQ11 M_B_A12 K32 B26 M_B_DQ11
M_A_A13 MA_ADD[12] MA_DATA[11] M_A_DQ12 M_B_A13 MB_ADD[12] MB_DATA[11] M_B_DQ12
AE27 MA_ADD[13] MA_DATA[12] E19 AF33 MB_ADD[13] MB_DATA[12] B21
M_A_A14 L26 H20 M_A_DQ13 M_B_A14 K33 A22 M_B_DQ13
M_A_A15 MA_ADD[14] MA_DATA[13] M_A_DQ14 M_B_A15 MB_ADD[14] MB_DATA[13] M_B_DQ14
[12] M_A_BS#[2..0] L27 MA_ADD[15] MA_DATA[14] E22 [13,14] M_B_BS#[2..0] J32 MB_ADD[15] MB_DATA[14] C24
D22 M_A_DQ15 B25 M_B_DQ15
M_A_BS#0 MA_DATA[15] M_B_BS#0 MB_DATA[15]
AB27 MA_BANK[0] AB33 MB_BANK[0]
M_A_BS#1 AA29 H25 M_A_DQ16 M_B_BS#1 AA32 A28 M_B_DQ16
M_A_BS#2 MA_BANK[1] MA_DATA[16] M_A_DQ17 M_B_BS#2 MB_BANK[1] MB_DATA[16] M_B_DQ17
[12] M_A_DM[7..0] M30 MA_BANK[2] MA_DATA[17] F25 K31 MB_BANK[2] MB_DATA[17] B28
D28 M_A_DQ18 B31 M_B_DQ18
M_A_DM0 MA_DATA[18] M_A_DQ19 MB_DATA[18] M_B_DQ19
D16 MA_DM[0] MA_DATA[19] D29 [13,14] M_B_DM0 C18 MB_DM[0] MB_DATA[19] A32
M_A_DM1 D20 E23 M_A_DQ20 B23 C26 M_B_DQ20
MA_DM[1] MA_DATA[20] [13,14] M_B_DM1 MB_DM[1] MB_DATA[20]
M_A_DM2 E25 D24 M_A_DQ21 C28 B27 M_B_DQ21
MA_DM[2] MA_DATA[21] [13,14] M_B_DM2 MB_DM[2] MB_DATA[2