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5 4 3 2 1
ZQ1 BLOCK DIAGRAM GPU CORE PWR
MAX8792ETD P41
CHARGER
ISL88731 P45
GPU IO PWR 3/5V SYS PWR
ISL62872 P42 RT8206 P36
D DISCHARGER CPU CORE PWR D
P44 ISL62882 P37
CLOCK GENERATOR Fan Driver
SELGO: SLG8LV595V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.8V P40/P44 CPU VTT
ARD: 1.05V
CFD: 1.1V
X'TAL
14.318MHz P3
P34 TPS54418RTE UP61111AQDD P38
CPU VGFX_AXG VTT 1.05V
DDR SYSTEM MEMORY
CPU ISL62881 P43 UP61111AQDD P39
Dual Channel Arrandale (SG)
DDR III XDP Conn.
800/ 1066 MHz P16
SO-DIMM 0 THERMAL DDR3 PWR
SO-DIMM 1 800 MT/s 1066 MT/s PROTECTION P46 RT8207A P40
P14, 15 rPGA 989
(37.5mm X 37.5mm)
PCI-E PCIE
X16 CRT
ATI GPU LVDS CRT P25
P4~P7 FDI DMI 2.5GT/s LVDS_CRT
Madison LP/PRO
HDD (SATA) 1GB (16 x 64Mb x 8pcs) INT_CRT Switchable
C
P29 INT_LVDS LVDS C
FDI interface X4 DMI interface P17~P24 P25 P25
X'TAL
ODD (SATA) SATA0 27.0MHz
Graphics Interfaces
FDI DMI
P29 INT_CRT HDMI
USB board SATA1 intel INT_LVDS
HDMI HDMI
INT_HDMI P26
Level-shift
USB Port X3 SATA PS8101 P26
USB 3 3.0 GT/s
USB 2.0 Ibex Peak_M RTC X'TAL
USB 9 P9 32.768KHz
USB 12 P32
PCI-E
PCI-Express
USB 2.5GT/s
USB Port x 1
USB 1 PCIE-1 PCIE-6 PCIE-2
(Debug)
P32
CLKOUT_PEG_B CLKOUT_PEG_2 CLKOUT_PEG_1
B
mBGA 25mm)
(27mm X
676 B
Bluetooth Atheros Mini Card Mini Card
USB 4 P32
Azalia HDA Giga-LAN
P8~P13 WiFi 3G
AR8151 P27 USB 13 P28 USB 10 P28
SPI LPC X'TAL USB10 USB13
CCD 25MHz
USB 8 P25
Transformer SIM Card FFC P28
P27
CardReader SPI ROM Conn
4MB x1 (Basic ME+Braidwood)
AU6437 P9 daughter board
Audio CODEC EC RJ45
USB 12 P31 USB5
RTL ALC271X
(NPCE781/783) P27
Note: P35
HM55 does not support USB 6 & 7 P30
X'TAL
HM55 does not support SATA 2 & 3 32.768KHz
A A
P34
SPDIF/HP INT MIC DMIC SPI ROM Touch Pad Keyboard Button on
3G@
PK@
FOR 3G SKU
FOR PARK GPU
P30 P30 P25 P35 P32 P34 mechanical key Quanta Computer Inc.
MD@ FOR MADSION GPU
IV@ FOR UMA
PROJECT : ZQ1
Size Document Number Rev
SW@ FOR SWITCHABLE GRAPHIC 1A
Block Diagram
Date: Wednesday, December 16, 2009 Sheet 1 of 48
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
B B
Power States Thermal Follow Chart
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
VIN +10V~+19V MAIN POWER S0~S5
+RTC_CELL +3V~+3.3V RTC S0~S5 NTC
+3VPCU +3.3V 8051 POWER ALWON S0~S5 Thermal
Protection
+5VPCU +5V CHARGE POWER ALWON S0~S5
+15V +15V LARGE POWER +15V_ALWP S0~S5
3V_LAN_S5 +3.3V LAN POWER AUX_ON
CPU H_ORICHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
+5VSUS +5V SUSD
CORE PWR H/W Throttling
CPU WIRE-AND SYS PWR
C C
+3VSUS +3.3V SUSD
+1.5V_SUS +1.5V SODIMM POWER SUSON
+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON SML1ALERT#
+5V +5V MAIND PCH FAN Driver FAN
+3V +3.3V MAIND
+1.8V +1.8V MAINON SM-Bus
+1.5V +1.5V PCH POWER MAIND
+1.1V_VTT +1.05V~+1.1V CPU POWER MAINON EC
CPUFAN#
+1.05V +1.05V PCH POWER MAINON
+VCC_CORE 0V~+1.5V CPU CORE POWER VRON
D D
LCDVCC +3.3V LCD Power LVDS_VDDEN
MBAT+ +10V~+17V MAIN BATTERY
Quanta Computer Inc.
+5V_S5 +5V S5_ON
PROJECT : ZQ1
+3V_S5 +3.3V S5D Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Wednesday, December 16, 2009 Sheet 2 of 48
1 2 3 4 5 6 7 8
5 4 3 2 1
CLK Gen(CLK) pi-filter
close PIN 1 close PIN 1, 17, 24 each U38 pi-filter
150mA(30mil)
+1.5V L54 595@BLM18AG601SN1D/200mA/600ohm_6 +1.5V_CLK 1 80mA(20mil)
VDD_DOT +VDDIO_CLK L58
17 VDD_SRC VDD_SRC_I/O 15 +1.05V
C746 C752 C758 C467 C789 24 18 BLM18AG601SN1D/200mA/600ohm_6
VDD_CPU VDD_CPU_I/O C790 C786 C794 C802
D 5 VDD_27 D
*0.1u/10V_4 R551 *585@0_6 *10u/6.3V_8 0.1u/10V_4 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK (10)
0.1u/10V_4 0.1u/10V_4 4 0.1u/10V_4 0.1u/10V_4 10u/6.3V_8 *0.1u/10V_4
9/22 modify DOT_96# CLK_BUF_DREFCLK# (10)
pi-filter CLK_SDATA 31
CLK_SCLK SDA R300 SW@33_4
20mil 32 SCL 27M 6 27M_CLK (18) Place each 0.1uF cap as close as
+3V L57 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 7 R301 *SW@0_4 possible to each VDD IO pin. Place
27M_SS 10/5 modify
the 10uF caps on the VDD_IO plane.
C792 R554 33_4 CPU_SEL 30 10
(10) CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL (10)
C754 C466 C757 11
SRC_1#/SATA# CLK_BUF_PCIE_3GPLL# (10)
*0.1u/10V_4 C772 27p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLK (10)
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 14
SRC_2# CLK_BUF_DREFSSCLK# (10)
1
XTAL_IN 28
B-test Y6 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R579 10K_4
close bead close PIN 5, 29 each XTAL_OUT *CPU_STOP#
2
C782 33p/50V_4 2 20
VSS_DOT CPU_1 TP46
8 VSS_27 CPU_1# 19 TP45
C 9 VSS_SATA CPU_0 23 CLK_BUF_BCLK (10) C
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# (10)
IDT: AL003197002 (ICS9LVS3197BKLFT) 21 VSS_CPU CK_PWRGD_R
26 25
Realtek: AL000890000 (RTM890N-632-GRT) 33
VSS_REF CKPWRGD/PD#
GND
Silego: AL000595000 (SLG8LV595VTR)
SLG8LV595V
+3V +3V CRB use +3VPCU
CPU_CLK select(CLK) SMBus(CLK)
+1.05V
CLK Enable(CLK)
R584
R563 1K_4
B B
2
R555 4.7K_4
*4.7K_4 CK_PWRGD_R
3 1 CLK_SDATA CLK_SDATA (14,15,28)
(10,16,28) ICH_SMBDATA
3
Q37
CPU_SEL Q33 2N7002K
2N7002K
(37) VR_PWRGD_CK505# 2 R580
R564 100K_4
4.7K_4 +3V
1
R558
2
4.7K_4
0 1
A
(10,16,28) ICH_SMBCLK 3 1 CLK_SCLK CLK_SCLK (14,15,28) Quanta Computer Inc. A
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q35
(default) 2N7002K PROJECT : ZQ1
Size Document Number Rev
1A
Clock Generator
Date: Friday, January 22, 2010 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1
Arrandale_1(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) Processor Compensation Signals
U28A U28B
B26 PEG_COMP R415 49.9/F_4 R490 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK (11)
MISC
MISC
A24 B27 R491 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# (11)
(8) DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 PEG_RBIAS R414 750/F_4
(8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] (17) R148 49.9/F_4 H_COMP1 G16 AR30 BCLK_ITP_P (16)
(8) DMI_TXN2 DMI_RX#[2] COMP1 BCLK_ITP
A21 K35 PEG_RXN0 AT30 BCLK_ITP_N (16)
D (8) DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP# D
J34 PEG_RXN1 R492 49.9/F_4 H_COMP0 AT26
PEG_RX#[1] PEG_RXN2 COMP0
(8) DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 PEG_CLK E16 CLK_PCIE_3GPLL (10)
D23 G35 PEG_RXN3 D16 CLK_PCIE_3GPLL# (10)
(8) DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
B23 G32 PEG_RXN4 AH24
(8) DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK (10)
(8) DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK# (10)
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK#
D24 D35