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Information about cable, connector or adapter : Communication and Networking Riser (CNR)

 Communication and Networking Riser (CNR)
 Originally developed by :
 Copyright :
 Source :
 Category :   All cables and connectors > Connectors > Computer > Buses >
 Added to database : 2005-07-12 04:15:00
 Description : Communication and Networking Riser (CNR)

 Communication and Networking Riser (CNR)
 

 Pinout :
PinNameDirectionColorDescription
A1MII_MDCManagement data clock signal from Management Data Controller to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this
B1MII_MDIOManagement data input/output signal between the Management Data Controller and the MII compliant PHY. This signal is used to carry bi-directional data for control and status registers. For detailed information on this signal, refer to the current version
A2MII_CRSCarrier sense signal from the MII compliant PHY to the MAC. This signal indicates that there is traffic on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Speci
B2MII_COLCollision detect signal from the MII compliant PHY to the MAC. This signal indicates that a collision has occurred on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 8
A3GNDPower supply and signal ground return path.
B3MII_TXCData clock from the MAC to the MII compliant PHY. For detailed information, refer to the current version Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current
A4MII_RXDVReceive data valid signal from the MII compliant PHY to the MAC. This signal indicates that valid data is available on the MII_RXD[3:0] signals. For detailed information on this signal, refer to the current version of the Core Logic Design Specification a
B4GNDPower supply and signal ground return path.
A5MII_RXCData clock from a MII Interface compliant PHY to the MAC. For detailed information, refer to the current version Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the
B5MII_RXERRReceive error signal from the MII compliant PHY to the MAC. This signal indicates that an error has occurred during frame reception. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE
A6GNDPower supply and signal ground return path.
B6MII_TXD3Bit 3 (MSB) of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of t
A7MII_TXD2Bit 2 of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this si
B7GNDPower supply and signal ground return path.
A8MII_TXD0Bit 0 (LSB) of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of t
B8MII_TXD1Bit 1 of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this si
A9GNDPower supply and signal ground return path.
B9MII_TXENTransmit enable signal from the MAC to the MII compliant PHY. This signal indicates that the available on the MII_TXD[3:0] signals can be placed on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Desig
A10RESERVEDRESERVED
B10GNDPower supply and signal ground return path.
A11MII_RXD1Bit 1 of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this si
B11MII_RXD2Bit 2 of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this si
A12MII_RXD3Bit 3 (MSB) of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of t
B12MII_RXD0Bit 0 (LSB) of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of t
A13USB+Positive side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B13GNDPower supply and signal ground return path.
A14GNDPower supply and signal ground return path.
B14RESERVEDRESERVED
A15USB-Negative side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B15+5VdualPositive 5-volt main/standby power supply (can be used for USB power). +5Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When a +5Vdual supply is not available
A16+12VPositive 12-volt main power supply
B16USB_OC#USB bus over-current signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
A17GNDPower supply and signal ground return path.
B17GNDPower supply and signal ground return path.
A18+3.3VdualPositive 3.3-volt main/standby power supply. +3.3Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When +3.3Vdual is not available, this pin must be connected to
B18-12VNegative 12-volt main power supply
A19+5VDPositive 5-volt main digital power supply
B19+3.3VDPositive 3.3-volt main digital power supply
A20GNDPower supply and signal ground return path.
B20GNDPower supply and signal ground return path.
A21EE_DININThis signal carries serial data from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board. The EE_DIN signal on the CNR connector must be connected to the DIN pin on the Microwire
B21EE_DOUTOUTThis signal carries serial data from the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board to the core logic MAC Microwire* interface. The EE_DOUT signal on the CNR connector must be connected to the DOUT pin on the Microwi
A22EE_CSINThe CNR board uses this signal to enable the serial EEPROM devices on the CNR board. When EE_CS is high (one) the Microwire EEPROM (for the LAN Interface) becomes active. When EE_CS is low (zero) the EEPROM is inactive. The resting state of this signal is
B22EE_SHCLKINThis signal is the serial clock signal from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board.
A23SMB_A1INThis signal is bit 1 of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B23GNDPower supply and signal ground return path.
A24SMB_A2INThis signal is bit 2 (MSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B24SMB_A0INThis signal is bit 0 (LSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address of the CNR board.
A25SMB_SDAIN/OUTBi-directional serial data line between the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet
B25SMB_SCLINSerial clock line from the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet the current versi
A26AC97_RESET#Active low AC TM97 link reset signal. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC 97 Component Specification.
B26CDC_DN_ENAB#CDC_DN_ENAB# indicates whether the motherboard or the CNR is in control, or mastering, the AC TM97 interface attached to the CNR Connector. When at a logic low level, the CDC_DN_ENAB# signal indicates that the primary codec on the motherboard is active an
A27RESERVEDRESERVED
B27GNDPower supply and signal ground return path.
A28AC97_SDATA_IN1AC TM97 serial data from an AC TM97-compliant codec (primary or secondary) to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requ
B28AC97_SYNCSynchronization pulse from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the AC link. This signal is nominally a 1.3 µS wide pulse, which is used to synchronize the AC link. For detailed information, refer to the current versi
A29AC97_SDATA_IN0AC TM97 serial data from a primary AC TM97-compliant codec to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the
B29AC97_SDATA_OUTAC TM97 serial data from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the link. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requi
A30GNDPower supply and signal ground return path.
B30AC97_BITCLKSerial data clock from primary codec to AC TM97 Controller and any non-primary codecs. The nominal frequency of this signal is 12.288 MHz. For detailed information, refer to the current version of the AC TM97 Component Specification. AC97_BITCLK is an out

 Note : Communication and Networking Riser (CNR) TYPE B
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