File name x_ref_wire_c.txt!M_BL1PWM c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_BL0PWM c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SSCLKI c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCD c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT0 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT1 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCMD c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDCLK c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT2 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDWP c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_SDDAT3 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_UART_KEYREQ c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO18 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_STC0PWM c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_COLDRST c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_STC0CLKI c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_CLKX c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO21 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO20 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_VBIINT c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!V_ACHIPINT1 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!S_EUARTINT c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!P_LANINT c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!D_PODINT c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO04 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO02 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO00 c_u01_seine2[101]sylph_clk_rst_etc.(pe0140).html U01 SEINE2 [101] SYLPH CLK/RST etc. (PE0140)
!M_PIO59 c_u01_seine2[102]sylph_iic_uart_scif(pe0140).html U01 SEINE2 [102] SYLPH IIC/UART/SCIF (PE0140)
!S_USBCLKXO c_u01_seine2[102]sylph_iic_uart_scif(pe0140).ht |