datasheets 74ls113 free download

File name 74ls113.pdf

SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K DUAL JK NEGATIVE inputs may be allowed to change when the clock pulse is HIGH and the EDGE-TRIGGERED FLIP-FLOP bistable will perform according to the truth table as long as minimum setup times are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY negative-going edge of the clock pulse. LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 1 Q Q 5(9) 6(8) N SUFFIX PLASTIC CASE 646-06 SET (SD) 14 4(10) K 1 J 3(11) 2(12) 1(13) CLOCK (CP) D SUFFIX SOIC 14