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M28010 1 Mbit (128K x 8) Parallel EEPROM With Software Data Protection PRELIMINARY DATA s s Fast Access Time: 100 ns Single Supply Voltage: ­ 4.5 V to 5.5 V for M28010 ­ 2.7 V to 3.6 V for M28010-W ­ 1.8 V to 2.4 V for M28010-R 32 s s s Low Power Consumption Fast BYTE and PAGE WRITE (up to 128 Bytes) Enhanced Write Detection and Monitoring: ­ Data Polling ­ Toggle Bit ­ Page Load Timer Status PDIP32 (BA) 1 s s s s s s JEDEC Approved Bytewide Pin-Out Software Data Protection Hardware Data Protection Software Chip Erase 100000 Erase/Write Cycles (minimum) Data Retention (minimum): 10 Years PLCC32 (KA) TSOP32 (NA) 8 x 20 mm DESCRIPTION The M28010 devices consist of 128Kx8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics' proprietary double polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply (5V, 3V or 2V, depending on the option chosen). Table 1. Signal Names A0-A16 DQ0-DQ7 W E G VCC VSS Address Input Data Input / Output Write Enable Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 W E G M28010 Chip Enable Output Enable Supply Voltage Ground VSS AI02221 January 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/22 M28010 Figure 2A. DIP Connections DU A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 M28010 25 24 23 22 21 20 19 18 17 AI02222 Figure 2C. TSOP Connections VCC W DU A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A11 A9 A8 A13 A14 DU W VCC DU A16 A15 A12 A7 A6 A5 A4 1 32 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 8 9 M28010 25 24 16 17 AI02224 Note: 1. DU = Do Not Use Note: 1. DU = Do Not Use Figure 2B. PLCC Connections A12 A15 A16 DU VCC W DU 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7 9 M28010 25 data retention. The organization of the data in a 4 byte (32-bit) "word" format leads to significant savings in power consumption. Once a byte has been read, subsequent byte read cycles from the same "word" (with addresses differing only in the two least significant bits) are fetched from the previously loaded Read Buffer, not from the memory array. As a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. By careful design of the memory access patterns, a 50% reduction in the power consumption is possible. SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A16). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip E