Catalyst Semiconductor CAT28C65B free download

File name 28C65B.pdf

CAT28C65B CAT28C65B 64K-Bit CMOS PARALLEL EEPROM FEATURES s Fast read access times: s Commercial, industrial and automotive ­ 90/120/150ns s Low power CMOS dissipation: temperature ranges s Automatic page write operation: ­ Active: 25 mA max. ­ Standby: 100 µA max. s Simple write operation: ­ 1 to 32 bytes in 5ms ­ Page load timer s End of write detection: ­ On-chip address and data latches ­ Self-timed write cycle with auto-clear s Fast write cycle time: ­ Toggle bit ­ DATA polling ­ RDY/BUSY BUSY s 100,000 program/erase cycles s 100 year data retention ­ 5ms max s CMOS and TTL compatible I/O s Hardware and software write protection DESCRIPTION The CAT28C65B is a fast, low power, 5V-only CMOS parallel EEPROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, a RDY/BUSY pin and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C65B features hardware and software write protection. The CAT28C65B is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDECapproved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages. BLOCK DIAGRAM A5­A12 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING, TOGGLE BIT & RDY/BUSY LOGIC COLUMN DECODER 5099 FHD F02 I/O0­I/O7 A0­A4 RDY/BUSY ADDR. BUFFER & LATCHES © 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1009, Rev. A Doc. No. 1009, Rev. A CAT28C65B PIN CONFIGURATION DIP Package (P) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SOIC Package (J, K) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N) A7 A12 RDY/BUSY TSOP Package (8mm x 13.4mm) (T13) NC VCC WE NC A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 A8 A9 A11 NC OE A10 CE I/O7 I/O6 OE A11 A9 A8 NC WE VCC RDY/BUSY A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 28C65B F03 I/O1 I/O2 VSS PIN FUNCTIONS Pin Name A0­A12 I/O0­I/O7 CE OE RDY/BSY Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Ready/Busy Status Pin Name WE VCC VSS NC Function Write Enable 5 V Supp