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File name:74ls109.pdf
[preview 74ls109]
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Model:74ls109 🔎
Original:74ls109 🔎
Descr: . Electronic Components Datasheets Various datasheets 74ls109.pdf
Group:Electronics > Other
Uploaded:27-07-2020
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File name 74ls109.pdf

SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D DUAL JK POSITIVE flip-flop by simply connecting the J and K pins together. EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM SET (SD) 5(11) Q CLEAR (CD) 6(10) J SUFFIX 1(15) CERAMIC CLOCK CASE 620-09 4(12) 16 1 Q 7(9) J 2(14) K N SUFFIX 3(13) PLASTIC 16 CASE 648-08 1 D SUFFIX SOIC 16 1 CASE 751B-03 MODE SELECT -- TRUTH TABLE INPUTS OUTPUTS OPERATING MODE ORDERING INFORMATION SD

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