datasheets 74173 free download

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54173 DM54173 DM74173 TRI-STATE Quad D Registers June 1989 54173 DM54173 DM74173 TRI-STATE Quad D Registers General Description These four-bit registers contain D-type flip-flops with totem- To minimize the possibility that two outputs will attempt to pole TRI-STATE outputs capable of driving highly capaci- take a common bus to opposite logic levels the output con- tive or low-impedance loads The high-impedance state and trol circuitry is designed so that the average output disable increased high-logic-level drive provide these flip-flops with times are shorter than the average output enable times the capability of driving the bus lines in a bus-organized sys- tem without need for interface or pull-up components Features Gated enable inputs are provided for controlling the entry of Y TRI-STATE outputs interface directly with system bus data into the flip-flops When both data-enable inputs are Y Gated output control lines for enabling or disabling the low data at the D inputs are loaded into their respective flip- outputs flops on the next positive transition of the buffered clock Y Fully independent clock elminates restrictions for oper- input Gate output control inputs are also provided When ating in one of two modes both are low the normal logic states of the four outputs are Parallel load available for driving the loads or bus lines The outputs are Do nothing (hold) disabled independently from the level of the clock by a high Y For application as bus buffer registers logic level at either output control input The outputs then Y Typical propagation delay 18 ns present a high impedance and neither load nor drive the bus line Detailed operation is given in the function table Y Typical frequency 30 MHz Y Typical power dissipation 250 mW Y Alternate Military Aerospace device (54173) is avail- able Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram