CERN 1101700 V1 DS22 Functional Description free download

File name 1101700_V1_DS22_Functional_Description.pdf

22bit Sigma-Delta ADC Theory and Circuit Operation J. G. Pett Introduction A basic Sigma-Delta ADC is shown in Fig.1 and has an action essentially the same as a Charge-Balance type. This is termed a 1st order modulator. Additional integrators can be added between the first integrator and the comparator, where Fig.2 shows a 3rd order modulator. The following sections explain firstly the basic theory of operation of a SD type of ADC and then give a detailed description of the modulator circuit. The digital filter is described in the final section. Theoretical Concepts Oversampling Any ADC can be described as an electronic circuit that quantises a given input signal. This means that the digital output has a number of output codes, each of which describes a particular interval of the input signal. For a perfect ADC of n bits, each interval will be equal to Vfsr/ 2n [Vfsr = the full-scale range of the input signal]. If a perfect transition from one output code to the next occurs as the input signal increases, then it becomes possible to interpolate between each interval using averaging techniques and hence improve the resolution beyond that of the n bit ADC. Such methods are termed oversampling. [In practise, the input signal must frequently traverse at least two adjacent intervals to ensure correct averaging. This is assured for most cases by the signal noise, the ADC internal noise or an externally applied "dither" signal, which sweeps the input over a narrow range of bit intervals, or transitions.] Normal averaging of 10 output values allows each interval to be divided by 10, effectively increasing the resolution by more than 3bits, but this requires sampling the signal 10 times faster to retain the same signal bandwidth. Alternatively, we can express this as reducing the quantising "noise", or uncertainty. Averaging 100 values will improve the noise by 40dB and so on. Oversampling by 500 will reduce the quantisation noise by 54dB, however this also means that ADC bandwidth is traded against improved resolution. Consider an example from the 22bit ADC. For a 1kHz bandwidth signal to digitise, we must sample at 2kHz [Nyquist criteria]. If we now oversample at 1MHz to improve the resolution, we will obtain approx. 9 extra bits of resolution and improve the signal to noise ratio by 54dB. [Note : the definition of oversampling ratio is fs/fNyquist.] Noise Shaping Provided that the input signal is not a stationary [DC] value, the above quantisation noise can be described as 'white noise' with a bandwidth of fs/2. The basic Sigma-Delta modulator is a form of charge-balance ADC having a 1bit quantiser [the comparator] and a 1bit very-high-precision DAC. The quantisation noise is that coming from the 1bit DAC and is large [N/S is approximately 0dB]. This noise is integrated by the TE EPC first integrator and hence modifies the theoretical white noise spectrum, re