cray T-0202- 1S Computer System IO Subsystem Station Operators WorkbookTraining-UNDATED.OCR free download

File name T-0202-CRAY_1S_Computer_System_IO_Subsystem_Station_Operators_WorkbookTraining-UNDATED.OCR.pdf

! CRAY-I S. COnpUTER SYSTCil liD SUBSYSTE~ STATION OPERATOR'S ~ORKBOOK T-0202 CHAPTER 1 1/0 SUBSYSTEM HARDWARE OVERVIEW INPUT/OUTPUT SUBSYSTEM INCREASES CRAY-! S CPU THROUGHPUT BY REDUCING ITS 1/0 AND FRONT-END RESPONSIBILITIES. STREAMS DATA TO CENTRAL MEMORY OVER AN 810 MBIT/S CHANNEL. ' PROVIDES ACCESS TO ADDITIONAL PERIPHERALS. (TAPES) FUNCTIONS AS A MAINTENANCE CONTROL UNIT. DRIVES UP TO 48 DD-29 DISK DRIVES FOR MASS STORAGE. ALLOWS OPERATOR CONTROL OF COS. COLLECTS AND CONCENTRATES DATA FROM FRONT-ENDS. PROVIDES FOR JOB AND DATA ENTRY. DISTRIBUTES CPU OUTPUT TO SLOWER PERIPHERAL EXPANDER DEVICES. CONSISTS OF TWO TO FOUR 1/0 PROCESSORS WITH A SHARED BUFFER MEMORY. 1.2 :E W t- (/) >- (/) CQ :::J (/) 0 ... ~ ~ ~ I - ~ ~ W 0::: :::J t9 ~ LL INDIVIDUAL 1/0 PROCESSOR LOCAL MEMORY: 65 536 WORDS J 16 BITSIWORD 2.43 GIGABIT BAND WIDTH COMPUTATION SECTION: INSTRUCTION CONTROL NETWORK 2 FUNCTIONAL UNITS (ADDER AND SHIFTER) LOGICAL 'AND' OPERATION 512 OPERAND REGISTERS 1 PROGRAMMER-VISIBLE ACCUMULATOR SINGLE ADDRESS MODE 76 MEGAHZ CYCLE TIME 1/0 SECTION: 6 DIRECT MEMORY ACCESS (DMA) PORTS 810 MEGABIT/S MAXIMUM TRANSFER RATE PER PORT SEVERAL CHANNELS MAY MULTIPLEX INTO ONE PORT 1.4 MODEL NUMBERING CONVENTION CRAY-l S/1200 THROUGH 14400 CONTAIN AN 1/0 SUBSYSTEM FIRST DIGIT INDICATES SIZE OF CENTRAL MEMORY IN MEGAWORDS SECOND DIGIT INDICATES NUMBER OF 1/0 PROCESSORS EXAMPLE: CRAY-l S/2300 HAS 2 MILLION WORDS OF CENTRAL MEMORY AND 3 1/0 PROCESSORS. 1.5 CRAY-! S/x300 THREE PROCESSOR SYSTEM 1. MASTER 1/0 PROCESSOR (MIOP) CONTROLS FRONT END-INTERFACES. HAS THREE DISPLAY CONSOLES. HAS AN EXPANDER CHANNEL WHICH MULTIPLEXES A PRINTER AND A MAG TAPE UNIT. CONNECTS TO BUFFER MEMORY THROUGH A DMA CHANNEL. EXCHANGES CONTROL SIGNALS WITH CPU OVER A LOW-SPEED CRAY-! S CHANNEL PAIR. COMMUNICATES WITH OTHER lOPs OVER ACCUMULATOR CHANNELS. MAINTAINS SYSTEM INFORMATION ERROR LOG. COORDINATES ACTIONS OF CPU AND OTHER lOPs. 2. BUFFER I/O PROCESSOR (BIOP) HANDLES DATA TRANSFERS BETWEEN CPU AND I/O SUBSYSTEM CONNECTS DIRECTLY TO CENTRAL MEMORY. CONNECTS TO BUFFER MEMORY THROUGH A DMA CHANNEL. COMMUNICATES WITH OTHER lOPs OVER ACCUMULATOR CHANNELS. DRIVES UP TO