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MODEL SL308 VERSION V_0.00 PREPARED BY H/W DATE 17/11/2005 SUBJECT TECHNICAL MANUAL PAGE 1/33 Baseband section This document provides a description of the baseband section of the SL308. Most design decisions are explained, but no detailed calculations are included. Total chip solutions(MT6218, MT6305, MT6129) except for RF Power Amplifier(RF3146) are from Media Tek, Taiwan. I. MT6218 ( GSM/GPRS Baseband Processor ) Figure 1. Block Diagram of MT6218 Figure 1 details the block diagram of MT6218. Based on dual-processor architecture, the major processor of MT6218 is ARM7EJ-S, which mainly runs high-level GSM/GPRS protocol software as well as multi-media applications. With the other one is a digital signal processor corresponding for handling the low-level MODEM as well as advanced audio functions. Except for some mixed-signal circuitries, the other building blocks in MT6218 are connected to either the microcontroller or the digital signal processor. SL308 TECHNICAL MANUAL MODEL SL308 VERSION V_0.00 PREPARED BY H/W DATE 17/11/2005 SUBJECT TECHNICAL MANUAL PAGE 2/33 Figure 2. Typical Application of MT6218 1. Micro-Controller Unit Subsystem ARM7EJ-S, plays the role of the major bus master controlling the whole subsystem. Essentially, it communicates with all the other on-chip modules by way of system buses : AHB Bus and APB Bus. All bus transactions originate from bus masters, while slaves can only respond requests from bus masters. Prior to a data transfer can be established, bus master must ask for bus ownership. This is accomplished by request-grant handshaking protocol between masters and arbiters. Two levels of bus hierarchy are designed to provide alternatives for different performance requirements, i.e. AHB Bus and APB Bus for system back bone and peripheral buses, respectively. To have high performance and proper efficiency, the AHB Bus provides 32-bit data path with multiplex scheme for bus interconnections. Only memory addressing method is used in MT6218 based system. All components are mapped onto MCU 32-bit address space. A Memory Management Unit is employed to have a central decode scheme. It generates certain selection signals for each memory-addressed modules on AHB Bus. In order to off-load the processor core, a DMA Controller is designated to act as a master and share the bus resources on AHB Bus to do fast data movement between modules. This controller comprises thirteen DMA channels. A 512KByte SRAM is provided for acting as system memory for high-speed data access. For fac