File information: | |
File name: | 18cv8p.pdf [preview PEEL 18CV8P] |
Size: | 403 kB |
Extension: | |
Mfg: | ICT |
Model: | PEEL 18CV8P 🔎 |
Original: | 18CV8P 🔎 |
Descr: | This is the PEEL 18CV8P Datasheet |
Group: | Electronics > Components > Integrated circuits |
Uploaded: | 11-10-2006 |
User: | bin_imad |
Multipart: | No multipart |
Information about the files in archive: | ||
Decompress result: | OK | |
Extracted files: | 1 | |
File name 18cv8p.pdf ® International Commercial/ CMOS Technology Industrial PEELTM 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic s Multiple Speed Power, Temperature Options - 74 product terms x 36 input AND array - VCC = 5 Volts ±10% - 10 inputs and 8 I/O pins - Speeds ranging from 5ns to 25 ns - 12 possible macrocell configurations - Power as low as 37mA at 25MHz - Asynchronous clear - Commercial and industrial versions available - Independent output enables s CMOS Electrically Erasable Technology -- 20 Pin DIP/SOIC/TSSOP and PLCC - Superior factory testing - Reprogrammable in plastic package s Application Versatility - Reduces retrofit and development costs - Replaces random logic s Development / Programmer Support - Super sets PLDs (PAL, GAL, EPLD) - Third party software and programmers - Enhanced Architecture fits more logic than ordinary - ICT PLACE Development Software and PDS-3 PLDs programmer - PLD-to-PEEL JEDEC file translator General Description The PEEL18CV8 is a Programmable Electrically Erasable The PEEL18CV8 architecture allows it to replace over 20 Logic (PEEL) device providing an attractive alternative to standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro- ordinary PLDs. The PEEL18CV8 offers the performance, vides additional architecture features so more logic can be flexibility, ease of design and production practicality needed put into every design. ICT's JEDEC file translator instantly by logic designers today. converts to the PEEL18CV8 existing 20-pin PLDs without the need to rework the existing design. Development and The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC programming support for the PEEL18CV8 is provided by and TSSOP packages with speeds ranging from 5ns to popular third-party programmers and development software. 25ns with power consumption as low as 37mA. EE-Repro- ICT also offers free PLACE development software and a grammability provides the conv |
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