Intel Present P6 Microarchitecture Details free download

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Intel Corporation 2200 Mission College Blvd. P.O. Box 58119 Santa Clara, CA 95052-8119 News Release INTEL PRESENTS P6 MICROARCHITECTURE DETAILS Technical Paper Highlights "Dynamic Execution" Design SAN FRANCISCO, Calif., Feb. 16, 1995 -- Intel Corporation today disclosed details of the first fruit of a parallel engineering effort, the next-generation P6 microprocessor, at an engineering conference here. The presentation of technical details follows the delivery of first working samples to OEMs. The 5.5-million transistor chip will deliver the highest level of processor performance for the Intel Architecture when systems using the chip begin to ship in the second half of this year. P6 will achieve this performance using a unique combination of technologies known as Dynamic Execution. P6 microarchitecture details were presented by Intel at the IEEE International Solid State Circuits Conference (ISSCC), an annual industry gathering where technical innovations are showcased and discussed. Details on P6's unique approach to high-performance processing, described collectively as Dynamic Execution, were presented by Dr. Robert Colwell, P6 architecture manager, at ISSCC. Colwell explained that this architectural enhancement is the next step beyond the superscalar advance implemented in the Pentium