Sony CDX-3183 free download

File name CDX-3183.pdf

CDX-3183 4-4. SCHEMATIC DIAGRAM -- CD MECHANISM SECTION -- · Refer to page 22 for Waveforms and Note and page 37 for IC Block Diagrams. (Page 33) ­ 25 ­ ­ 26 ­ CDX-3183 4-6. SCHEMATIC DIAGRAM -- DISPLAY SECTION -- (Page 36) Note: · All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums. · All resistors are in and 1/4 W or less unless otherwise specified. · U : B+ Line. · Power voltage is dc 14.4V and fed with regulated dc power supply from ACC and BATT cords. · C : panel designation. · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM · Voltages are taken with a VOM (Input impedance 10 M). Voltage variations may be noted due to normal production tolerances. ­ 29 ­ ­ 30 ­ CDX-3183 4-8. SCHEMATIC DIAGRAM -- MAIN SECTION (1/2) -- · Refer to page 39 for IC Block Diagrams. (Page 26) (Page 35) Note: · All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums. · All resistors are in and 1/4 W or less unless otherwise specified. ў · : internal component. · C : panel designation. · U : B+ Line. · Power voltage is dc 14.4V and fed with regulated dc power supply from ACC and BATT cords. · Voltage is dc with respect to ground under no-signal (detuned) condition. no mark : FM ( ) : MW · Voltages are taken with a VOM (Input impedance 10 M). Voltage variations may be noted due to normal production tolerances. · Signal path. F : FM f : MW J : CD ­ 33 ­ ­ 34 ­ CDX-3183 4-9. SCHEMATIC DIAGRAM -- MAIN SECTION (2/2) -- · Refer to page 34 for Note and page 39 for IC Block Diagrams. (Page 34) (Page 29) ­ 35 ­ ­ 36 ­ · IC Block Diagrams IC1 CXD2507AQ XLON SPOD SPOC SPOB SPOA CLKO VDD XLTO DATO CNIN SEIN CLOK XLAT 64 63 62 61 60 59 58 57 56 55 54 53 52 FOK MON MDP MDS LOCK TEST FILO FILI PCO VSS AVSS CLTV AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 SERVO AUTO SEQUENCER 5 14 CPU INTERFACE SUB CODE PROCESSOR 4 DIGITAL CLV DIGITAL PLL EFM DEMODULATOR 51 50 49 48 47 46 45 44 43 42 41 40 DATA XRST SENS MUTE SQCK SQSO EXCK SBSO SCOR VSS WFCK EMPH 3 ASYMMETRY CORRECTOR 5 D/A INTERFACE DIGITAL OUT CLOCK GENERATOR 39 DOUT 38 37 36 35 34 C4M FSTT XTSL XTAO XTAI RF BIAS ASYI ASYO ASYE 14 15 16 17 18 16K RAM ERROR CORRECTOR 3 6 WDCK 19 33 MNTO 20 21 22 23 24 25 26 27 28 29 30 31 32 LRCK PCMD BCLK GTOP XUGF XPCK VDD GFS RFCK C2PO XROF MNT3 MNT1 CH3-IN CH2-IN IC3 BA6796FP-T1 OP IN ­ OP IN + CH1-IN CH1 + CH1 ­ VREF CH3 CH2 CH2 + CH2 ­ VCC CH1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LEVEL SHIFT VCC LEVEL SHIFT DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER LEVEL SHIFT THERMAL SHUT DOWN LEVEL SHIFT LOGIC CTL1 CTL2 FWD REV V/I DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER 1 OPOUT 2 CH4-IN 3 CH4 4 CTL1 5 CTL2 6 FWD 7 REV 8 TRAY 9 GND 10 CH5 ­ 11 COM 12 CH4 + 13 CH3 + 14 CH3 ­ ­ 37 ­ IC2 CXA1782BQ PHD 2