File information: | |
File name: | Force 1030-00003-4.rar [preview 1030-00001] |
Size: | 192 kB |
Extension: | |
Mfg: | Force |
Model: | 1030-00001 🔎 103000001 |
Original: | 1030-00001 🔎 |
Descr: | Force 1030-00001 DVB Receiver |
Group: | Electronics > Satellite equipment |
Uploaded: | 29-04-2004 |
User: | plamensl |
Multipart: | No multipart |
Information about the files in archive: | ||
Decompress result: | OK | |
Extracted files: | 1 | |
File name Force 1030-00003-4.pdf 5 4 3 2 1 PCB1 Revision list: 99.07.02 First release of partlist 99.07.05 Complex 27Mhz circuit replaced by oscillator #1030-19003 D D BC847 1 1 B E C Transistor Footprint GND1 C gnholed C MT1 1 MT3 1 1 MountingHole 1 MountingHole TH1 1 TH2 1 TH3 1 FM1 1 1 FM2 1 1 1 Toolinghole 1 Toolinghole 1 Toolinghole Fiducial Fiducial B B PINS FOR MAC MODULES MT4 1 MT5 1 MT6 1 MT7 1 1 1 1 1 HFC2580-Hole HFC2580-Hole HFC2580-Hole HFC2580-Hole A A All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion. Mechanical 5 4 3 2 Title 1030 Mechanical Parts Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000 1 Sheet 1 Rev 1.0 of 9 5 4 3 2 1 Micro&Mac Scart FRONTEND-CA D BBVIDEO BBVIDEO BBVIDEO I2CSCL I2CSDA /D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V C MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio MACPAL ROUT GOUT BOUT MACYOUT MACCOUT MacLeftAudio MacRightAudio D /D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V /D_WAIT D_RD/WR /D_CS2 /INT0 -RESET3.3V CLK 27MHZ TSCA_CLK TSCA_START TSCA_VALID TSCA_D[0..7] DA[2..23] DD[0..7] /D_BE2 /D_BE3 /RESET5V YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L YDIG CDIG CVBSDIG RDIG GDIG BDIG FBL DIG-AUD-R DIG-AUD-L C SmartCardIf 50HZ 50HZ 50HZ Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A 50HZ Vpp low -Power A -Power B Vpp A Vpp B Card I/O A Card Clock A Card Reset A I2CSCL I2CSDA I2CSCL I2CSDA I2CSCL I2CSDA IR RX SCART IR RX SCART IR RX SCART SCTX SCRX SCTX SCRX SCTX SCRX B B Card I/O B Card Clock B Card Reset B Card det A Card det B Card I/O B Card Clock B Card Reset B Card det A Card det B 50HZ Card I/O B Card Clock B Card Reset B Card det A Card det B 50HZ Power 50HZ A A All information contained on this drawing is copyright of FORCE Electronics A/S Denmar k. Legal actions will be taken against any company u sing or copying the design/ideas or information contai ned on this drawing without prior written permiss ion. " ÃH6DI 5 4 3 2 Title DVB Receiver Document Number Size 1030-00003-4 A3 Date: Thursday, January 20, 2000 1 Sheet 2 Rev 1.0 of 9 5 4 3 2 1 6 TSCA_D[0..7] TSCA_D[0..7] U1 TSCA_D7 TSCA_D6 TSCA_D5 TSCA_D4 TSCA_D3 TSCA_D2 TSCA_D1 TSCA_D0 3.3V C1 100nF 20 10 18 16 14 12 9 7 5 3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 74LVX244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 2 4 6 8 11 13 15 17 1 19 MIBPB7 MIB |
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