Intel 440BX free download

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A B C D E Intel 100 MHz Pentium(tm) II processor/440BX AGPset Uniprocessor Customer Reference Schematics 4 Revision 1.0 ** Please note that these schematics are subject to change. 4 TITLE COVER SHEET BLOCK DIAGRAM SLOT 1 CONNECTOR CLOCK SYNTHESIZER 82443BX 3 PAGE 1 2 3,4 5 6,7,8 9,10,11 12,13 14 15 16,17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 B C THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES W H A T S O EVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. *Third-party brands and names are the property of their respective owners. Copyright * Intel Corporation 1997, 1998 3 DIMM SOCKETS PIIX4E ULTRA I/O AGP CONNECTOR PCI CONNECTORS ISA CONNECTORS IDE CONNECTORS USB CONNECTORS FLASH BIOS 2 PARALLEL SERIAL/FLOPPY KEYBOARD/MOUSE VRM POWER CONNECTOR GTL+ TERMINATION PCI/AGP PULLUPS/PULLDOWNS ISA PULLUPS/PULLDOWNS 82443BX DECOUPLING 2 INTEL CORPORATION PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 Title Intel 100MHz Pentium(tm) II processor/440BX AGPset Uni-Processor Cover Sheet Size A Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 D 1 BULK DECOUPLING TERMINATION DECOUPLING LM79 REVISION HISTORY A 1 Rev 1.0 1 E Sheet of 34 1 2 3 4 5 6 7 8 VRM VTT GEN. PG. 25 A P E N T I U M (tm) II PROCESSOR (SLOT 1) PG. 3,4 CK100 & ITP CON. PG. 5 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER P R O DUCT. iNTEL IS NOT RESPONSIBLE FOR THE MISUSE O F THIS INFORMATION. A SMBus Interface MAX1617 ME PG. 3 DEVICE TABLE SYSTEM BUS ADDR ADDR CNTL CNTL DATA DATA GTL TERM. PG. 27 DEVICE TYPE FUSES REFERENCE DESIGNATOR F1,F2,F3,F4 PAGE # 20,24 ITP Connector DIMM Sockets CNTL J2 J4,J5,J6 J12, J13 J14, J15 J16, J17 J24 J33 A,B J32 J34-37 5 9,10,11 18 19 20 25 3,4 15 16,17 B MEMORY 3 SDRAM DIMM MODULES PG. 9-11 ISA Connectors IDE Connectors USB Connectors VRM8.2 Slot 1 Connector AGP Connector ADDR/DATA AGP C O N N. ADDR CNTL 82443BX 492 BGA CKBF PG. 6 DATA AGP SIDEBAND PG. 15 B PG. 6-8 PCI Connectors BLM31A700S CNTL L1-L6,L7-L13 20,24 ADD/DATA CK100 U1 3VSB U5 A,B,C,D,E,F U6 U7 A,B,C,D,E,F U8 A,B,C,D,E,F U9 U12 A,B,C,D,E,F U13 5 13,26 14 15,26,29 2