free download

File name Pillar Rock laptop schematic diagram (Intel Montevina Mobile platform).pdf

5 4 3 2 1 PILLAR ROCK Table of Contents Page D Montevina Mobile Platform CUSTOMER REFERENCE BOARD Merom Fab 3 Rev. 1.0 Description TITLE PAGE NOTES Penryn (1 of 2) Penryn (2 of 2) CPU Thermal Sensor CANTIGA (1 OF 6) CANTIGA (2 OF 6) CANTIGA (3 OF 6) CANTIGA (4 OF 6) CANTIGA (5 OF 6) CANTIGA (6 OF 6) CANTIGA STRAP & CAMARILLO DDR2 SODIMM 0 DDR2 SODIMM 1 DDR2 TERMINATION CRT LVDS TVO PCIE GRAPHICS XDP ICH9M (1 of 4) ICH9M (2 of 4) ICH9M (3 of 4) ICH9M (4 of 4) PCI-E Slots (1 & 2) PCI-E Slots (3,4 & 5) High Definition Audio HDA Power Supply USB 1.1/2.0 SATA (1 of 3) SATA (2 and 3 of 3) PCI Edge Connector(Gold finger) LAN Boaz LAN Docking and SPI CK505 DB800 & Buffers FWH and I/O Port Expander SIO Legacy Support H8 2116 KBC(1 of 2) H8 2116 KBC(2 of 2) PS2 LPC Slot, TPM Header, DOCKING TPS51120 SYSTEM POWER VR DDR2 VR CANTIGA VR DDR VREF GRAPHICS CORE VR SYSTEM CHARGER VR SYSTEM CHARGER BATTERY IMVP-6 CONTROLLER IMVP-6 DRIVERS&FETS CPU Decoupling DISCHARGE CIRCUITS Start Up Sequence Sleep control POWER SEQUENCING C B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 A 5 w w w la . 4 to p -s p h c m e ic t a .c s m o D C B Pillar Rock Title TITLE PAGE Size A Date: 3 Intel Confidential A Document Number 355659 Tuesday, August 28, 2007 2 Rev 1.0 Sheet 1 1 of 58 5 4 3 2 1 MONTEVINA CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D Voltage Rails POWER PLANE +VBATA +VBAT +VBATS +V12S -V12A -V12S +V5A +V5 +V5S +V3.3A +V3.3M +V3.3M_CK505 +V3.3 +V3.3S +V1.8 +V1.5S +V1.05M +V1.05S +V0.9 +VCC_CORE +VCC_GFXCORE VOLTAGE 6V-14.1V 6V-14.1V 6V-14.1V 12V -12V -12V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.5V 1.05V 1.05V 0.9V 0.35V-1.5V 0.7V-1.25V ACTIVE IN S0/M0, S0/M0, S0/M0 S0/M0 S0/M0, S0/M0 S0/M0, S0/M0, S0/M0 S0/M0, S0/M0, S0/M0, S0/M0, S0/M0 S0/M0, S0/M0 S0/M0, S0/M0 S0/M0, S0/M0 S0/M0 (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, (S3-S5)/M-off S3/M1, S3/M-off (S3-S5)/M1, (S3-S5)/M-off (S3-S5)/M1, S3/(M-off w/WOL_EN) (S3-S5)/M1 S3/M1, S3/M-off (S3-S5)/M1, S3/M-off (S3-S5)/M1 (S3-S5)/M1, S3/M-off GMCH, ICH core, and FSB rail DDR command & control pull up. CPU core rail GMCH Graphics core rail LAN Clock, MCH DDR core DESCRIPTION Battery Battery Battery Only on Only on Only on Rail in Mobile Power Mode Rail in Mobile Power Mode Rail in Mobile Power Mode in DT Power Mode in DT Power Mode in DT Power Mode I 2 C / SMB Addresses Address 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 xxxx 0111 001x 0011 110x 1001 100x 1001 101x 0001 110x 0001 111x 0011 000x 0011 001x 1001 100x TBD TBD TBD TBD TBD TBD TBD TBD Hex D2 DC A0 A4 30 34 4C 3x 72 3C 98 9A 1C 1E 30 32 98 TBD TBD TBD TBD TBD TBD TBD TBD Bus SMB_ICH_M3 SMB_ICH_M3 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH_M2 SMB_ICH ALS EMA SMB_THRM SMB_THRM SMB_BS SMB_BS S