Ergo free download

File name Ergo laptop motherboard schematic diagram.pdf

BLOCK DIAGRAM Dothan 478 uFCPGA 1,2 CLOCK GEN. ICS950815 6,7 HOST BUS AGTL 1.3V,100MHZ LCD_CN 17 Montara855GME CRT 16 DDR SDRAM 333MHz 732 uFCBGA 8,9,10,11 USB 1 34 Hublink 66MHZ USB2.0 IDE_BUS USB 2 34 CDROM SWAP BAY 32 HDD_CN 32 FDD LPC, 33MHz SUPER I/O PC87393 37 w w w IR 38 LPT 38 p la . KEYBOARD CONTROLLER M3885XHP 39 INTERNAL KEYBOARD&TP 40 s p to ICH4-M 421 BGA 16,17,18,19 AC LINK AC97 STAC9700T m e h c DDR333 SODIMM X 1 +2.5V +1.25V 14 256/ 512 Mb DDR X 8 12,13 a ic t .c s 15 29 m o CAP/RES ... DDR PCI_BUS 3.3V, 33MHz CARDBUS RICOH R5C590 26 LAN REALTEK 8101 MINI PCI TYPEII 31 23 Mic pre. AMP MDC 25 25 AUDIO AMP 24 CARDBUS 1 SLOT VCCA, VCCB VPPA, VPPB 27,28 LAN IO 30 FWH 41 EAR OUT 24 MIC. IN 24 RJ11 1394 SLOT 27 A B C D E +VCCP 9 1 2,3,5,9,10,11,18,19,20,50 H_A#[31:3] U34A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 U3 R2 P3 T2 P1 T1 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 C2 D3 A3 C6 D1 D4 B4 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0 REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 A20M# FERR# IGNNE# ADS# BNR# BPRI# DEFER# DRDY# DBSY# N2 L1 J3 L4 H2 M2 N4 A4 B5 J2 B11 H1 K1 L2 M3 K3 K4 C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7 B17 B18 A18 C17 H_BPM0_ITP# H_BPM1_ITP# H_BPM2_ITP# H_BPM3_ITP# H_BPM4_PRDY# H_BPM5_PREQ# H_TCK H_TDI H_TDO ITP_DBRESET# H_RS#0 H_RS#1 H_RS#2 H_IERR# H_INIT# 18,41 9 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# 9 9 9 9 9 9 9 +VCCP H _ T D I pullup (R8001) must b e p laced within 300ps of C P U TDI pin (within 2") R379 56 +VCCP CONTROL BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ# TCK TDI TD0 TMS TRST# DBR# R382 54.9 P lace testpoint o n H_IERR# with a GND 0.1" away H_LOCK# H_RS#[2:0] H_TRDY# H_HIT# 9 H_HITM# 9 9 9 9 H_ADSTB#0 H_REQ#[4:0] H_CPURST# 9 9 +VCCP ITP SIGNALS 2 TP2 TP7 TP5 TP3 TP61 TP58 H_TCK R383 +VCCP 150 5 R390 56 THERM 9 18 18 18 18 18 5 18 3 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# THERMTRIP# PM_THRMTRIP# CLK_ITP_CPU# CLK_ITP_CPU CLK_CPUHCLK# CLK_CPUHCLK 6 19 6 6 6 A15 STPCLK# ITP_CLK1 A16 LINT0 ITP_CLK0 B14 LINT1 BCLK1 B15 SMI# BCLK0 Banias-Processor-Skt_cooperspur H CLK R388 10K R387 10K Layout note: C O M P 0 a n d C OMP2 need to be Zo=27.4ohm traces. B e s t e s t i m a t e i s 18mil wide trace for outer layers and 1 4 m i l i f o n internal layer. See RDDP of Banias. T r a c e s s h o u l d b e shorter than 0.5". Refer to latest CS layout C O M P 1 , C O M P3 should be routed as Zo=55ohm t r a c es shorter than 0.5" 4 Comp0 Comp1 Comp2 Comp3 5 w w w R243 54.9_1% R244 27.4_1% p