Sony MBX-229 free download

File name Sony_MBX-229_-_WISTRON_CADIZ-CP_-_REV_-1M.pdf

5 4 3 2 1 SYSTEM DC/DC CADIZ-CP Block Diagram Clock Generator D PROJECT CODE : 91.4JH01.001 PCB P/N : 48.4JH01.01M REVISION : 09941-1M RT8223 INPUTS 5V_S5(9A) DCBATOUT 37 OUTPUTS 3D3V_S5(5A) 5V_AUX_S5 D ICS9LVS3197BKLFT 3 3D3V_AUX_S5 DDRIII 800 DDRIII 800 Slot 0 21 Slot 1 22 DDRIII Channel A Intel CPU PCI EXPRESS GRAPHIC X16 Thermal Sensor GMT G787 30 DDRIII Channel B SFF 4,5,..,10,11 FDIx8 DMIx4 ATI Park-S3/ M93-S3 58...62 RT8209 VRAM DDR3 1Gb*4 63...66 INPUTS DCBATOUT 39 OUTPUTS 1D05V_S0(20A) Int MIC RT8209 CRT/B LVDS 38 OUTPUTS 1D5V_S3(13.5A) Codec Line Out C INPUTS DCBATOUT Realtek ALC275SQ 28 AZALIA LCD INTEL RGB 19 CRT HDMI 25 RT9026 INPUTS 5V_S5 MIC In SPKR 1.5W PCH 14 USB 2.0/1.1 ports ETHERNET (10/100/1000Mb) 36 C PCIe USB Port x 1 CAMERA SIM USB USB Port x 2 Mini2 Card WWAN PCIe PCIe Mini 1 Card WLAN/ WIMAX Giga LAN Atheros AR8131M OUTPUTS DDR_VREF_S3 1.2A High Definition Audio 6 SATA ports MS/MS Pro /MS Pro HG SD/MMC Card Cardreader Ricoh R5U231 PCIe 8 PCIE ports ACPI 1.1 LPC I/F PCI/PCI BRIDGE CHARGER BQ24751 INPUTS 23 32 OUTPUTS CHG_PWR 18V 6.0A MINI/B DCBATOUT Express Card TPS2231 USB Blue Tooth 28 CPU DC/DC ADP3211 INPUTS 36 B 1394 B OUTPUTS 27A CARDREADER/B VCC_CORE DCBATOUT FeliCa HDD SATA 24 Flash ROM 4MB 32 SATA SPI 32 VGA/ GFX Core ADP3211 40 12,13,...,19,20 TXFM RJ45 27 INPUTS OUTPUTS DCBATOUTVGA_CORE/ LPC VCC_GFXCORE 11A PCB STACKUP TOP GND S S VCC S GND BOTTOM 5 KBC L1 L2 L3 L4 L5 L6 L7 L8 Winbond NPCE781L 31 SPI A Flash ROM 128KB 32 LPC DEBUG CONN.32 SMbus ADDRESS DIMM 1 DIMM 2 CLK GEN Thermal Sensor CHARGER BATTERY 1010 000x b 1010 001x b 1110 001x b 0101 110x b 0001 001x b 0001 110x b 2 Squirtle CP DIS SAMSUNG A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Touch Pad 24 4 INT. KB 31 3 BLOCK DIAGRAM Size A3 Date: Document Number Rev CADIZ-CP Saturday, April 24, 2010 Sheet 1 -1M 1 of 57 A B C D E PCH Strapping Name SPKR Processor Strapping Schematics Notes Pin Name CFG[4] Strap Description Embedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples. 4 INIT3_3V# GNT3#/ GPIO55 INTVRMEN GNT0#, GNT1# Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k - 10-k weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k pull-down resistor). Configuration (Default value for each bit is 1 unless specified otherwise) 1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1: Single PCI-Express Graphics 0: Bifurcation enabled Clarksfield (only for early s