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File name U50SI1 Schematics RevC.pdf

5 4 3 2 1 U50SI1 Schematics Rev:C PAGE D CONTENT D 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. C Cover Page System Block Diagram POWER BLOCK DIAGRAM & Sequence GPIO & POWER CONSUMPTION CPU HOST & CPU Thermal Sensor CPU_POWER NB_672MX_HOST_PCIE NB_672MX_DRAM NB_672MX_MuTIOL_VGA NB_672MX_PWR_GND DDR2_SO-DIMM SB_968_PCI_IDE_MuTIOL_SPI SB_968_PCIE_LAN_GPIO U50SI1 REV:C P/N LIST PCB P/N PCB ASSY P/N C 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. B SB_968_USB_SATA SB_968_PWR_GND CLK_GEN & CLK_BUFFER SIS 307LV_LVDS_TV EC IT8512 / BIOS / KB CONN PWR SW / LED / LCD / TP HDD / ODD / USB / Mini Card CRT / FAN / Smart Power CARD READER(RTS5158) LAN PHY(RTL8201CL) CODEC & AMP/INT_MIC/SPK EXT_MIC / HEADPHONE BATT IN / Charger DC IN/RTC/Discharger/APC +5V/+1.8V (ISL6227) CPU_CORE (ISL6262A) LDO 3.3VA/1.8V/1.5V/1.2V/1.05V VCC SW/ WEBCAM Change Notes B 27. 28. 29. 30. 31. 32. A A Elitegroup Computer Systems Title Cover Page Size Date: 5 4 3 2 Document Number 3255 Tuesday, July 31, 2007 1 Rev C Sheet 1 of 32 5 4 3 2 1 U50SI1 SYSTEM BLOCK DIAGRAM D CRYSTAL 14.318MHz CPU Celeron M Socket P 5,6 D THERMAL ADM1032 5 EC CRT Main Clock Gen. ICS9LPR600 16 Host Bus 667/800 MHZ DDR2 Clock Buffer ICS9P935 16 DDR2 RAM BUS CRT 21 DDR2-SODIMM0 11 533/667MHZ North Bridge SIS M672 7,8,9,10 PCIE x16 SIS 307ELV 17 LVDS LCD 19 MuTIOL 1G Media I/O CRYSTAL 14.318M HZ C AUDIO CODEC ALC662 24 AZALIA IDE X 133 C DVD/CD 20 South Bridge RTC AMPLIFIER APA2068 24 GMAC Headphone Out x 1 Mic / Line In x 1 INT Mic x 1 MDC 32.768K SiS 968 12,13,14,15 RTL8201CL LAN PHY 23 RJ45 23 GMAC USB x 8 CRYSTAL 25M HZ INTERAL SPK 1.5W x 2 RJ11 USB x 4 USB CONN x 4 20 USB x 1 USB x 1 Mini Card 20 RTS5158 Card Reader 22 B B CRYSTAL LPC BUS SMBus Diagram 2.5" SATA HDD SB_SMB_DATA 20 12MHz SATAII x 1 Debug CONN 18 South Bridge 16,17,18,19 SB_SMB_CLK DDR DIMM 11 SPI EC K/B CONTROLLER ITE8512 18 CRYSTAL 32.768K FLASH ROM SMBus 0 18 BATTERY 30 Thermal Sensor for CPU EC A INT K/B SMBus 1 24 18 T/P 19 FAN 21 CHARGER 26 BATTERY 26 A Clock Gen 7 Elitegroup Computer Systems Title SYSTEM BLOCK DIAGRAM Size Date: 5 4 3 2 Document Number 3255 Tuesday, July 31, 2007 1 Rev C Sheet 2 of 32 5 4 3 2 1 POWER BLOCK DIAGRAM Adaptor or Battery POWER Sequence VINSW +5V_BOOT +5VA,+3VA S0 Max:500ms (1) SW_PWR_ON (2) +3.3VS_ON D VIN D +5V_BOOT LDO L78L05 VIN AO4468 (+3.3V_ON) SW_PWR_ON# VIN (+5V_BOOT) +5VA (+5V_ON) +5V . . (1) SW_PWR_ON (2) +3.3VS_ON VINSW AO4468 AO4469 +3VA AO4468 +3.3V (+5V_ON) . . (3) +1.8VS_ON +1.8VA +0.9V (4) AUX_PWRGD EC TO SB >10ms 10ms (3) +1.8VS_ON 1ms (4) AUX_PWRGD C C ISL6227 LDO APL1084 AO4468 VIN AO4468 RQA130N03 +1.8VA +1.8V +1.5V . . . . (5) PWRBTN# (6) PM_SLP_S4# (7) PM_SLP_S3# (8) +5V_ON +5V FROM +5VA EC TO SB SB TO EC SB TO EC 1s (5) PWRBTN# (6) PM_SLP_S4# (7) PM_SLP_S3# (8) +5V_ON 5.8ms 40ms AO4468 (+1.8VA_ON) (+1.8V_ON) LDO FIFT6137B +0.9V LDO FIFT6137B +3