Acer ASPIRE 5740 5740D 5340 free download

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5 4 3 2 1 JV50-CP Block Diagram D Project code: 91.4GD01.001 PCB P/N : 48.4GD01.0SB REVISION : SB 09285 CPU DC/DC ISL62882 INPUTS DCBATOUT OUTPUTS VCC_CORE 47,48 Clock Generator ICS9LRS3197AKLFT 3 DDRIII Slot 0 20 800/1066/1333 DDRIII Slot 1 21 800/1066/1333 DDRIII Channel A Arrandale Clarksfield 4~10 Intel CPU SYSTEM DC/DC PCI EXPRESS GRAPHIC X16 ATI Madison or Park 62~66 VRAM sDDR3 1Gb*8 67~70 TPS51123 INPUTS DCBATOUT 3D3V_S5 49 D OUTPUTS 5V_S5 DDRIII Channel B Digital Display SYSTEM DC/DC TPS51117 INPUTS DCBATOUT LVDS 1CH RGB CRT DMIx4 FDIx8 PCH RGB CRT OUTPUTS 1D5V_S3 50 Mini-Card 1 WLAN 37 Switch 22 CRT Switch 22 24 PCIE+USB 2.0 INTEL PCH LVDS 1CH SYSTEM DC/DC TPS51117 INPUTS DCBATOUT PCH Mini-Card 2 WLAN or 3G 37 C LCD WXGA+ Switch 25 23 OUTPUTS 1D05V_S0 50 14 USB 2.0/1.1 ports ETHERNET (10/100/1000Mb) High Definition Audio PCH Digital Display HDMI 25 SYSTEM DC/DC TPS51117 C RJ45 CONN INT MIC MIC IN LINE IN Giga LAN 31 6 SATA ports PCIE 30 WEBCAM 23 INPUTS DCBATOUT OUTPUTS 1D05V_VTT 51 8 PCIE ports ACPI 1.1 LPC I/F PCI/PCI BRIDGE USB 2.0 BCM57780 BLUETOOTH28 USB x 4 Card Reader AU6433 Touch Panel Finger Print 29 RT9025 INPUTS SD/MMC MS/MS Pro/xD 3D3V_S0 36 OUTPUTS 1D8V_S0 50 HD AUDIO CODEC ALC272 36 AZALIA 32 23 G2997 INPUTS 1D5V_S3 43 OUTPUTS 0D75_S0 52 LINE OUT&SPDIF SATA HDD B SYSTEM DC/DC ISL62881 26 INPUTS DCBATOUT OUTPUTS VCC_GFXCORE 54 B SATA 2CH SPEAKER OP AMP APA2031 33 SATA ODD 11~19 27 SYSTEM DC/DC TPS51117 INPUTS DCBATOUT SPI LPC Bus Flash ROM 4MB 40 41 OUTPUTS +VGA_CORE 55 MODEM RJ11 MDC CARD 35 LPC debug CHARGER KBC SPI PCB STACKUP 40 ISL88731A INPUTS DCBATOUT NPCE781B TOP GND OUTPUTS BT+ 53 A A ENG DIS MADSION SAMSUNG S Flash ROM 128KB 41 Thermal Sensor G787 39 Wistron Corporation Touch PAD 43 Int. KB40 S GND BOTTOM Title 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. FAN 5 4 3 Block Diagram Size A3 Date: 2 Document Number Rev JV50-CP Thursday, August 27, 2009 Sheet 1 SA 1 of 57 PCH Strapping Name SPKR A B Schematics Notes Processor Strapping Pin Name CFG[4] C D Default Value 1 E Strap Description Embedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples. Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k - 10-k weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k pull-down resistor). Configuration (Default value for each bit is 1 unless specified otherwise) 1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1: Single PCI-Express Graphics 0: Bifurcati