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File name: | 81-45416_Q200_Series_Programmers_Manual_Nov87.pdf [preview 81-45416 Q200 Series Programmers Manual Nov87] |
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Mfg: | quantum |
Model: | 81-45416 Q200 Series Programmers Manual Nov87 🔎 |
Original: | 81-45416 Q200 Series Programmers Manual Nov87 🔎 |
Descr: | quantum Q200 81-45416_Q200_Series_Programmers_Manual_Nov87.pdf |
Group: | Electronics > Other |
Uploaded: | 15-10-2019 |
User: | Anonymous |
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File name 81-45416_Q200_Series_Programmers_Manual_Nov87.pdf Q200 SERIESTM PROGRAMMER'S MANUAL QUANlUM CORPORATION 81-45416 REV ABC DA1E 01/87 04/87 11/87 EC 2021 2237 2407 ii PREFACE Quantum reserves the right to make changes and/or improvements to its products without incurring any obligation to incorporate such changes or improvements in units previously sold or shipped. Quantum publishes descriptive data sheets, a Product Description/OEM Manual, and a Technical Reference Manual for each product line. In addition, important changes to a product are conveyed in the form of a Technical Support Bulletin sent to all product customers of record. Those changes which alter manual content are covered by publishing Addenda to the affected manual. Quantum publications may be requested from your Quantum Sales Representative, or may be ordered from Quantum in the same manner as spare parts. Publication No. 81-45416, Rev. C Copyright 1986, 1987, 1988 Quantum Corporation. All rights reserved. AIRLOCK and Drs CACHE are registered trademarks of Quantum Corporation. Q200 Series is a trademark of Quantum Corporation. Printed in U.S.A. iii iv TABLE OF CONTENTS 1.0 SCOPE 1 2.0 APPLICABLE DOCUMENTS 1 3.0 GLOSSARY AND CONVENTIONS 1 3.1 GLOSSARY 1 3.2 EDITORIAL CONVENTIONS 2 4.0 INTERFACE CHARACTERISTICS 2 4.1 SCSI BUS 2 4.2 SCSI BUS SIGNALS 5 4.3 SCSI BUS TIMING 7 5.0 LOGICAL CHARACTERISTICS 8 5.1 SCSI BUS PHASES 8 5.1.1 BUS FREE Phase 8 5.1.2 ARBITRATION Phase 8 5.1.3 SELECTION Phase 9 5.1.4 RESELECTION Phase 10 5.1.5 Information Transfer Phases 11 5.1.6 COMMAND Phase 12 5.1.7 DATA Phase 12 5.1.8 STATUS Phase 13 5.1.9 MESSAGE Phase 13 5.1.10 Signal Restrictions Between Phases 14 5.2 SCSI BUS CONDmONS 14 5.2.1 ATTENTION Condition 14 5.2.2 RESET Condition 14 5.3 SCSI BUS PHASE SEQUENCES 15 5.3.1 Nonarbitrating Systems 15 5.3.2 Arbitrating Systems 15 5.3.3 All Syst |
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