HP HP-Bench-Briefs-1976-07-08 free download

File name HP-Bench-Briefs-1976-07-08.pdf

--- I TT-PACKARD JULY - AUGUST 1976 The sat ( lmd .re#t IR) inpuFs OyaCIjdo S aH a* input cQhrd8&mr: bc;ch ktpm tyva the paeMitv in&rtor to v h n b is ve"' low, the activehDgh outpu?is forced high; when "R" is low, the active-high output is forced low. Although normally the aotive-low output is drs complement of flipflops: W m n & h w?U sxta mfy for as long as both "8' and "R" wo brcl e J-K master/slave low. The flip-flop will return to some indeterminate state when both " S and "R" go high. DUAL DTYPE RIP-FLOP The duat D-type flip-flop shown in Figura I of two i m t D-tr.pe h flip-flops with inputs on the left and FIGURE 2 Four-Bit Bistable Latch . input. -flops. Inputs to the tion is derived as follows: master section on the left side are - The "DC" input has a AND n controlled by the gate (G) pulse. The gate relationship with the "C" input w pulse also controls the state of the shown by the subswipted "C". FOUR-BIT BISTABLE LATCH coupling transistors (not shown) wh Therefore, Data passas through "Dc" connect the mmw a r d m pd The fourbit bistable latch shown in only when " ' active trua 6 is Figure 2 consists of four independent - Input "C" is sensitive to transition, or D-type flip-flops. FFI and FF2 are sensitive as shown by controlled by the 61 dock input,