Samsung sdiag-7 free download

File name sdiag-7.pdf

Schematic Diagram 7. Schematic Diagram 7-1 Circuit Description Logic Board Y Main Board X Main Board Display Row PDP Panel DRAM Data Driver 42" - 1024x768 Pixels Input 1024x768x3 Cells (R,G,B) X-Pulse Data 50" - 1360x768 Pixels Data Display Generator Controller Driver 1360x768x3 Cells (R,G,B) Processor Timing Y-Pulse Timing Controller Generator Scan Timing Address Buffer SMPS Board LVDS Main SMPS Main Board LVDS Image Audio Deinterlacer Trans Enhancer Processor Image CPU Video Speaker Decoder Decoder Out AC Power Scaler RF Tuner Source Splitter TMDS A/D Video Converter S/W Micom Recever SMPS Board The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter has been used. For the other outputs, a Flyback converter has been used. LOGIC Board The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC. - LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.)