HP 98642 HP-DIO Four Channel Mux Firmware IMS May86 free download

File name 98642_HP-DIO_Four_Channel_Mux_Firmware_IMS_May86.pdf

/ / / HEW LET T / / / / PACKARD / / / / / / / HP-DIO FOUR CHANNEL TERMINAL MULTIPLEXER FIRMWARE INTERNAL MAINTENANCE SPECIFICATION (IMS) HEWLETT PACKARD COMPANY MAY 9, 1986 Roseville Networks Division 8000 Foothills Boulevard Elizabeth Poteet Roseville, California 95678 A-98642-90014-1 PAGE 2 of 51 ones; BITS a, BITS 1, BITS 2, BITS 3. Each of these is set with the bits to strip on incomIng characters according to the data in the most recent configuration change interrupt for that port. FILES CHANGED - MX VAR - Took out declaration for BITS_MSK; added BITS_a, BITS_1, - BITS_2, and BITS_3. MX4INIT - Took out initialization for BITS MSK. Initialized BITS_a, BITS_l, BITS_2, and BITS_3 instead. MX4RX - Added parameter to RX macro for the bits mask variable. RXERR - Same as MX4RX; added parameter to RX macro for bits mask variable. MX4TX - Took BITS MSK out of the extrn area. I don't know where it was used or why it was there in the first place. Probably an oversight. MXSBR - The routine, HSTCON, now passes the bits per character mask value back to. the calling routine instead of setting the value in the BITS MSK variable as before. MXPTO, MXPT1, MXPT2, MXPT3 - These routines now receive the bits per character mask value in the A register after HSTCON has finished execution and returned. They then save the mask value in the appropriate variable location for that port. MX4EQUS - The RX macro was changed to include the bit mask variable. RELIABILITY IMPROVEMENT (1/89 - Randy stout - Production Engineer) BRIEF DESCRIPTION - INTERMITTENT BUG IN SELF TEST SYMPTOM - The 98642 would occasionally (frequency ranging from 1 failure in 10 passes to 1 failure in 800 passes) fail it's on-board Self Test. REASON - Contrary to the published information, Zilog's CTC chip requires a Reset before interrupts are enabled. Issuing the Reset and the Enable Interrupt in the same control word can lead to a race condition on the chip. If there is an interrupt pending AND the Interrupt Enable occurs before the RESET, the CTC will issue a Z80 Interrupt. This combination occurred during the SIO Test portion of the Self Test, leading technicians to believe the SIO was at fault. The board would often pass Self Test with the