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File name: | gx18.1.1_errata.pdf [preview gx18.1.1 errata] |
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Mfg: | AMD |
Model: | gx18.1.1 errata 🔎 |
Original: | gx18.1.1 errata 🔎 |
Descr: | AMD gx18.1.1_errata.pdf |
Group: | Electronics > Other |
Uploaded: | 14-03-2020 |
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File name gx18.1.1_errata.pdf AMD GeodeTM GX1 Processor Silicon Revision 8.1.1 Specification Update 1.0 Scope This document discusses known issues of the AMD date, etc. However, the "A" in the 5th character is constant. GeodeTM GX1 processor, silicon revision 8.1.1. Table 1-1 Software can detect this revision by reading the DIR1 Con- provides a summary of the issues. A detailed description of figuration register (see Configuration registers in the GX1 each issue, its impact, and a recommended resolution/fix data book). The value read from DIR1 is 81h for silicon follow. revision 8.1.1. To determine the silicon revision of the device, printed on Silicon errata are tracked separately. This document per- the chip (bottom-side of SPGA, top-side of EBGA) is the lot tains to silicon revision 8.1.1 only. code number. The lot code number for silicon revision 8.1.1 Note: This is revision 8.1 of this document. The change is a 10-digit number with an "A" in the 5th character (e.g., from revision 8.0 (dated May 2002) is in format V8SKA040AG). Note that the other characters of the lot only. No technical changes. code number may change depending upon lot number, Table 1-1. Errata Summary Issue #1 Description 1 Incorrect CURRENT_IP field in SMI header 2 RSM truncates page-granular CS limit 3 SDRAM CAS latency of 1 not supported 4 VIH change from 2.0V to 2.1V on FLT# input 5 PCI AD bus floats too early on some target terminated cycles, not PCI 2.1 compliant 6 Memory writes in SMI handler could have A20 in their address cleared 7 Double fault handled as general protection fault 8 Call ESP does not work 9 PCI signal SERR# asserts for two clocks, not one 10 PCI signal LOCK# ignored 11 PCI signal PERR# is floated instead of driven high on deassertion 12 PCI REQs must not go active during reset 13 CALL at beginning of Code Segment Call causes General Protection Fault 14 Self modifying code can cause PF 15 Time Stamp Counter stops during Suspend 17 WORD access to Port 23; Port 24 half of access goes off chip 19 Thermal diode does not work 20 PCI Master Latency Timer is broken 21 Data setup to PCLK does not meet specification 22 Data setup to VID_CLK does not meet specification 23 Video port limited to 133 MHz 24 Behavior of EFLAGS during INTR handling is not as expected 25 Graphics resolution of 128 |
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