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MMSll17 128K x 18 PDP-11 ADD-IN SEMICONDUCTOR MEMORY MANUAL MMSll17 USER MANUAL PRODUCT: MMSll17 Family Artwork Revisions A and B DOCUMENT: Edition A Revision 2 1 September 78 TABLE OF CONTENTS PARAGRAPH CHAPTER I. SPECIFICATIONS 1.0 Introduction 1.1 Option Designations 1.2 Pinout 1.3 Physical 1.4 Environmental Requirements 1.5 Compatibility 1.6 Storage Capacity 1.7 Bus Loading 1.8 Addressing 1.9 I/O Page Use As R/W Memory 1.10 Parity 1.11 Timing 1.12 Refresh Latency 1.13 Power Requirements CHAPTER II: THEORY OF OPERATION CHAPTER III: INSTALLATION 3.1 MMSll17 xxPC, Using the Internal Parity Controller 3.2 MMSll17 xxP (and MMSlll7 xxPC) Using External Parity Generator 3.3 MMSll17xx No Parity 3.4 Battery Backup Mode, All Modules CHAPTER IV: REPAIR AND WARRANTY i CHAPTER I. SPECIFICATIONS 1.0 INTRODUCTION This manual describes the specifications, installation and operation of the MMSll17 memory system. The MMSll17 is a family of single-card memory systems, designed for, and fully compatfble with, PDP-ll* Unibus* mini-computers. It is capable of storing up to 128 kilobytes of data on a single hex-height module. Parity storage as well as controller functions are optionally available on the same module. The power and signal pin-outs are compatible with any hex-SPC slot and thus obviate the need for a specific memory back panel. 1.1 OPTION DESIGNATIONS The several available options are designated with a 4 character suffix to the basic name as shown in the following table: TABLE 1: MMSll17 OPTION DESIGNATOR SUFFIX Typical Read Access Pari ty Opt; ons: Total Storage Capacity (in kilobytes) Time 32K B 64K C:> 96K () 128KB 290 nsec parity + controller -32-PC -34-PC -36-PC -38-PC parity data only -32-P -34-P -36-P -38-P no pari ty -32 -34 -36 -38 360 nsec parity + controller -42-PC -44-PC -46-PC -48-PC pari ty data only -42-P -44-P -46-P -48-P no parity -42 -44 -46 -48 I 1390 nsec parity + controller -52-PC -54-PC -56-PC -58-PC 1