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PJP1
ZZZ1 ZZZ3 ZZZ4 ZZZ5
45@ DCIN
PCB LA-6091P LS-6094P LS-6095P DC301008S00
D0DAZ@ D0DA@ D0DA@ D0DA@
1 1
ZZZ2 ZZZ6 ZZZ8 ZZZ7 ZZZ9 ZZZ10
PCB LA-6091P LS-6096P LS-6097P LS-6098P LS-6099P
E0DAZ@ E0DA@ E0DA@ E0DA@ E0DA@ E0DA@
Compal Confidential
2 2
NAVD0 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRII + NV OPTIMUS
3
2010-02-09 3
REV: 1.0
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2009/10/09 Deciphered Date 2010/10/09 Title
Cover Page
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NAVD0 LA-6091P
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 03, 2010 Sheet 1 of 46
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Clock Generator
Compal Confidential CK505 page 13
Model Name : NAVD0
File Name : LA-6091P CRT Conn.
1
page 15 1
RGB
Memory BUS(DDRII) DDRII-SO-DIMM
Pineview page 7
LCD Conn. LVDS FCBGA 559 1.8V DDRII 667
page 14 22x22mm
Thermal Sensor page 4,5,6
EMC1402
page 5
DMI
X2 mode
GEN1
USB USB Port X2
2
PCI-Express Tigerpoint HDA page 23
2
PCBGA360 BlueTooth
page 24
17x17mm SATA
page 17,18,19,20
CMOS CAM
page 14
VGA MINI Card x1 WLAN 10/100 Ethernet
HDD Conn.
N11M-OP2 3G AR8132L
page 21 3G
page 8,9,10,11,12 page 24 page 25 page 23
page 24
LPC BUS
HDMI Conn Transfermer
3
page 16 3
Audio Codec
ALC272
page 28
Card Reader
RJ45
Power ON/OFF DC/DC Interface
page 34
ENE UB6250
page 27
page 22
3VALW/5VALW
page 39
ENE KBC SPI
DC IN
page 36
KB926
page 29
0.89VP/0.9VSP
page 41 To Audio Board To Audio Board
BATT IN AMP & INT SD/MMC/MS
INT MIC HeadPhone &
page 37 Speaker 29
page page 28 MIC Jack
CONN page 27
1.8V/VCCP Int.KBD SPI ROM
page 29
page 40 page 32 page 31
CHARGER Touch Pad
page 38
4
page32 4
VGA CPU_CORE
page 42
DC/DC Interface
page 35
VGA_CORE/ Security Classification Compal Secret Data Compal Electronics, Inc.
1.5VSP Issued Date 2009/10/09 Deciphered Date 2010/10/09 Title
page 43 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAVD0 LA-6091P
Date: Wednesday, March 03, 2010 Sheet 2 of 46
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Voltage Rails External PCI Devices
Power Plane Description S1 S3 S5 DEVICE IDSEL # REQ/GNT # PIRQ
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89VS Graphic core power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2
+5VS 5V switched power rail ON OFF OFF 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Smart Battery 0001 011X b EMC1402 100_1100
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3
ICH7M SM Bus address 3
BOARD ID Table(Page 31) Device Address
VCC 3.3V Clock Generator 1101 001Xb
(SLG8SP556VTR)
Ra 100K DDR DIMMA 1010 000Xb
ID BRD ID Rb Vab-Min Vab-Typ Vab-Max
0 R01 (EVT) 0 0V 0V 0V
1 R02 (DVT) 8.2K 0.216V 0.250V 0.289V
NAVD0
2 R03 (PVT) 18K 0.436V 0.503V 0.538V
3 R10A (MP) 33K 0.712V 0.819V 0.875V
4 R01 (EVT) 56K 1.036V 1.185V 1.264V
5 R02 (DVT) 100K 1.453V 1.650V 1.759V
NAVE0
6 R03 (PVT) 200K 1.935V 2.200V 2.341V
7 R10A (MP) NC 2.500V 3.3V 3.3V
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2009/10/09 Deciphered Date 2010/10/09 Title
Notes List
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NAVD0 LA-6091P
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 03, 2010 Sheet 3 of 46
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5 4 3 2 1
<7> DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M <7> DDR_A_D[0..63]
U71A U71B
REV = 1.1
<7> DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 AH19 AD3 DDR_A_DQS0
DMI_RX0_R <7> DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 <19> AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DMI_RX#0_R F2 G1 DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RXN_0 DMI_TXN_0 DMI_TX#0 <19> <7> DDR_A_MA[0..14] DDR_A_MA_2 DDR_A_DM_0
DMI_RX1_R H4 H3 DDR_A_MA3 AK16
DMI_RXP_1 DMI_TXP_1 DMI_TX1 <19> DDR_A_MA_3
DMI_RX#1_R G3 J2 DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN_1 DMI_TXN_1 DMI_TX#1 <19> DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
<13> CLK_CPU_EXP# EXP_CLKINN EXP_RCOMPO DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
N6 L9 R162 AH12 AE3
<13> CLK_CPU_EXP EXP_CLKINP EXP_ICOMPI DDR_A_MA_11 DDR_A_DQ_7
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 EXP_TCLKINP RSVD_TP N11 T38 AJ10 DDR_A_MA_14 DDR_A_DQS#_1 AD7
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
<7> DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
<7> DDR_A_CAS# DDR_A_RAS# DDR_A_CAS# DDR_A_DQ_9 DDR_A_D10
<7> DDR_A_RAS# AK21 DDR_A_RAS# DDR_A_DQ_10 AE5
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 <7> DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD <7> DDR_A_BS1 DDR_A_BS2 DDR_A_BS_1 DDR_A_DQ_13 DDR_A_D14
L3 N2 <7> DDR_A_BS2 AK11 AB9
RSVD RSVD DDR_A_BS_2 DDR_A_DQ_14 DDR_A_D15
AD6
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 AD8
DDR_CS#0 DDR_A_DQS_2 DDR_A_DQS#2
<7> DDR_CS#0 AH22 DDR_A_CS#_0 DDR_A_DQS#_2 AD10
DDR_CS#1 AK25 AE8 DDR_A_DM2
<7> DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
091105 change CPU Part Number to SA00003M870 AJ21
DDR_A_CS#_2
AJ25 AG8 DDR_A_D16
DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
DDR_A_DQ_17 AG7
DDR_CKE0 AH10 AF10 DDR_A_D18
<7> DDR_CKE0 DDR_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 DDR_A_D19
<7> DDR_CKE1 AH9 AG11
C435 DMI_RX0_R DDR_A_CKE_1 DDR_A_DQ_19 DDR_A_D20
<19> DMI_RX0 1 2 AK10 DDR_A_CKE_2 DDR_A_DQ_20 AF7
AJ8 AF8 DDR_A_D21
0.1U_0402_10V7K DDR_A_CKE_3 DDR_A_DQ_21
AD11 DDR_A_D22
C436 M_ODT0 DDR_A_DQ_22 DDR_A_D23
1 2 DMI_RX#0_R AK24 AE10
<19> DMI_RX#0 <7> M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
0.1U_0402_10V7K M_ODT1 AH26
<7> M_ODT1 DDR_A_ODT_1 DDR_A_DQS3
AH24 AK5
C437 DMI_RX1_R DDR_A_ODT_2 DDR_A_DQS_3 DDR_A_DQS#3
1 2 AK27 AK3
C <19> DMI_RX1 DDR_A_ODT_3 DDR_A_DQS#_3 DDR_A_DM3 C
0.1U_0402_10V7K DDR_A_DM_3 AJ3
C438 DMI_RX#1_R DDR_A_D24
<19> DMI_RX#1 1 2 AH1
M_CLK_DDR0 DDR_A_DQ_24 DDR_A_D25
0.1U_0402_10V7K <7> M_CLK_DDR0 AG15 DDR_A_CK_0 DDR_A_DQ_25 AJ2
M_CLK_DDR#0 AF15 AK6 DDR_A_D26
<7> M_CLK_DDR#0 M_CLK_DDR1 DDR_A_CK_0# DDR_A_DQ_26 DDR_A_D27
<7> M_CLK_DDR1 AD13 AJ7
DDR_A_CK_1 DDR_A_DQ_27
Close to CPU <7> M_CLK_DDR#1
M_CLK_DDR#1 AC13 DDR_A_CK_1# DDR_A_DQ_28 AF3
AH2
DDR_A_D28
DDR_A_D29
DDR_A_DQ_29 DDR_A_D30