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HAIER
COLOR TELEVISION
SERVICE MANUAL
PART # TV-8888-34
HAIER AMERICA TRADING, LLC
www.haieramerica.com
1
Service Manual Haier
Service Manual
For P42S6A-C1 / P42S6A-C2
Features
Built in tuner
Digital interface(DVI 1.0)
Auto Pixel shift for reduce image sticking
Graphic and video double window
8W-2CH speaker out ,subwoofer out
PC/DVI input resolution up to 1280*1024
HDTV signal interface
Power management function
Haier group
Edition:2003.11.11
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Service Manual Haier
Content
Contents.....................................................................................2
2.Features..................................................................................3
3.Safety measures and Attention.................................................4
4.Block Diagram ..........................................................................5
5.IC description ............................................................................7
6.IC layout &power map...............................................................10
6.1 IC layout & power map(digital board) ................................10
6.2 IC layout & power map(analog board) ...............................11
7.Panel interface ......................................................................12
7.1 Output signal timing_60HZ................................................12
7.2 Output signal timing_50HZ.........................................12
7.3 Output signal timing diagram......................................13
7.4 LVDS bit mapping.....................................................14
7.5 Panel connect pin configuration...................................14
8.Power interface...............................................................15
9.Inspections on major Ics...................................................16
10.Bom list.......................................................................22
11.repair record.................................................................53
11.1Record sheet:for reference........................................53
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2.Features
Built in tuner
Digital interface(DVI 1.0)
Auto Pixel shift for reduce image sticking
Graphic and video double window
8W-2CH speaker out ,subwoofer out
PC/DVI input resolution up to 1280*1024
HDTV signal interface
Power management function
Motion adaptive 3D Y/C Separation for composite NTSC video
signal
4H adaptive comb filter for PAL composite video signal
Multi-stand color decoder PAL/NTSC/SECAM
Multi-stand video sync processing
Multi-stand sound process with Turbo sound
Video window on graphic background
Graphic window on video background
Independent scale factors in vertical and horizontal
Graphic signal full sync processing
Motion-weighted interpolation for video source
Bad-edit detection/correction
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3. Safety measures and Attention
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4. BLOCK DIAGRAM 74HC VPC_S_RST_N_51 01_CPU_RXD0
CPU
DVI_SCL 24C21 74HC PC/DVI_L/R 4052 02_CPU_TXD0
DVI_SDA PC_AUDIO_SEL_N 4052 CPU_VSYNC MSPG TL062 TA2024 RM1_IRQ_53 03_HDTV_SEL
S-Video_L/R 3450G CDT POWER_N_54 04_CPU_BHE_N
DVI_V 0x80 IR_INT1_55 05_CPU_WR_N
DVI_H CPU_HSYNC DTV_L/R IR_INT0_56 06_CPU_RD_N
CPU_UCS_N_57 07_ALE
DVI_RX2 + AD9887 DVD_L/R CPU_LCS_N_58 08_ARDY(3.3V)
DVI_RX2 - V_SUB_EN_N_59 09_S2
0x98 Video_L/R V_MAIN_EN_N_60 10_S1
DVI_RX1 + PIN_DET_N_62 11_S0
DVI_RX1 - Tuner_SIF 13_X1
PD_LVDS_N_65 14_X2
DVI_RX0 + KEY_EN_N_65 16_RM1_CLK_IN
DVI_RX0 - RM-1A SCL_TMR_68 17_25MHz_AD9887
D_IN[0:7] SDA_TMR_69 19~40_A[19:0]
D_IN[8:15] CPU_RST_N_71 42_WHB
D_IN[16:23] V_OE_N_72 43_WLB
G_Port
PC_V SCL_STB_73 44_HLDA
PC_H PC_AUDIO_SEL_N_74 45_HOLD(GND)
D_ACTIVE
SDA_STB_75 46_HW_MONITOR
DIN_CLK
PC_R ADG774 D_HSYNC SCL1_76 47_NMI(GND)
D_VSYNC SDA1_77 48_WRITE_PROTECT
DTV_Y CPU_D[0:15]_78~95 49_RM1_RST_N
PC_G R/Y_IN G_LED_N_96 50_RM1_CS_N
VIDEO_DET 74HC244 R_LED_N_97
DTV_Pb G/Pb_IN SVHS_DET CPU_TXD1_98 PCF P0_COMP1_DVD_SEL
PC_B DVD_DET CPU_D[0:7] CPU_RXD1_99 P1_MUTE
B/Pr_IN PIN_DET_N DTV_DET FLI_RST_N_100 8574T P2
DTV_Pr PC_DET P3
PC_SCL 24C21 R/G(SOG)_IN DVI_DET P4
PC_SDA 74HC02 THER_DET SCL1 P5
SDA1 P6
P7
KEY_EN_N 74HC02
DTV_Y BA7657 HDTV_SEL CPU_RD_N ENTER 74HC244
SOURCE TX1 MAX CPU_TXD0
(option) MENU RX1 232A CPU_RXD0
DTV_Pb VOL - TX2 CPU_RXD1
74ACT244 74ACT244 74ACT244 VOL + RX2 CPU_RXD1
CH -
DTV_Pr CH + PHONE_TX
POWER PHONE_RX
V_OE_N
TxOUT0 -
DS90C TxOUT0 + 10P A6V
DVD_Y BA7657 VPC_M_RST_N 74ACT244 V_Port FI_WE GND
VPC3230 V_IN[0:7] OP_A[0:23] 385 Analog A12V
(option) DVD_Y FLI2200 TxOUT1 - 31P_HF GND
MAIN PWR
DVD_Pb TxOUT1 + 12Vam
VPC_Y[0:7] 0xC0 74ACT244
DVD_Pb 12Vam
0x88 VPC_C[0:7]
OP_HSYNC GND
DVD_Pr DVD_Pr TxOUT2 - GND
VPC_VS V_VS
OP_VSYNC TxOUT2 + A33V
VPC_HS V_HS 74ACT244
COMP1_DVD_SEL GND
VPC_LLC1 VCLK
OP_ENABLE
VPC_FLD V_ACTIVE
TxOUT3 -
V_VALID
74LCX74 CLK_OUT TxOUT3 + 11P A5V
GND
DFF_FLD Digital D3.3V
S-Video_Y TEA6425 FLI_RST_N 74ACT244 PD_LVDS_N TxCLKOUT- D3.3V
PWR
S-Video_C VPC3230 SUB_Y[0:7] TxCLKOUT+ GND
0x96 GND
3D_Y SUB NC
3D_C C 74ACT244 POWER_N
0x8E SUB_C[0:7]
GND_STB
Video_CVBS SCL_TMR PCF SCL_STB 24C16 STB_5V
(option) SUB_VS
Y SDA_TMR 8573T SDA_STB THER_DET
SUB_HS
AIR Tuner SUB_LLC2
Tuner_CVBS CVBS
0xC2 SUB_FLD
3D_Y UPD V_MAIN_EN_N V_SUB_EN_N
AFT 3D_C 64083
0xB8 CVBS
PCF SCL1 VPC_S_RST_N 5/57
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Service Manual Haier
5. IC DESCRIPTION
Name Package Description Manufacture
KIA78D05F DPAK Regulator KEC
KIA78D09F DPAK Regulator KEC
LP3961EMP-2.5 SOT 223-5 Regulator NATIONAL
LM1086ISX_3.3V TO-263 Regulator NATIONAL
LP3961EMP-1.8 SOT 223-5 Regulator NATIONAL
MICOM
1) Multiplexed address and data bus which is
compatible with 80c186 microprocessor
R8820LV PQFP 80 RDC
2) Supports nonmultiplexed address bus[A19 : A0]
3) 1M byte memory address space
4) 64K byte I/O Spaec
M29W160DB TSOP FLASH MEMORY ST
M24C16 SOP 8 EEPROM ST
74VHC08 SOP 8 2 input AND Gate FAIRCHILD
RGB Graphics Processing
Scan Converters
Aanlog Interface
1) 140 MSPS Maximum Conversion Rate
2) 330 MHz Analog Bandwidth
3) Full sync processing
AD9887KST MQFP ANALOG DEVICES
4) Midscale Clamping
5) 4:2:2 Output Format Mode
Digital Interface
1) 112MHz Operation(2pixels/clock mode)
2) High skew tolerance of 1 full input clock
3) Sync Detect for "hot plugging"
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Name Package Description Manufacture
LVDS Transmitter NATIONAL
+3.3V Programmable LVDS Transmitter 24-BIT Flat Panel
DS90C385 TSSOP
Display Link-85 MHz , +3.3V Programmable LVDS Transmitter
18-Bit Flat Display Link-85 Mhz
MAX821 SOT143 Power-on Reset MAXIM
74AHC244 SOP Octal Buffer and Line Driver PHILIPS
74VHC02 SOP Quad 2-Line NOR Gate FAIRCHILD
74LCX74 TSSOP D-Type Flip-Flop ST
Comb Filter Video Processor MICRONAS
1) High-performance adaptive 4H comb filter Y/C separator
With adjustable vertical peaking
2) Multi-standard color decoder PAL/NT/SECAM
VPC3230D QFP 3) Line-locked clock, data and sync, or 656-output interface
4) peaking,contrast, brightness,color saturation and
tint for RGB/YCrCb and CVBS/S-VHS
5) PIP processing for picture sizes whit 8 bit resolution
6) 15 predefined PIP display configuration and expert mode
Digital component video deinterl FAROUDJA
1) Motion-adaptive video deinterlacing selects optimal
filtering on a per-pixel basis
2) Supports 525/60(NTSC), 625/50(PAL/SECAM)
FLI2200 TQFP 3) Accepts up to 1100 pixels/line
4) 8/10-bit , 16/20-bit YUV,24/30-bit RGB or YCbCr/YPbPr
Progressive output option
5) High-order filtering produces smooth chroma output in
4:2:2 to 4:4:4 or 4:4:4 to 4:2:2 conversion
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Name Package Description Manufacture
MAX232ACSE SOP RS232 Transceivers MAXIM
TCPS9091PD27A tuner Tuner SEC
24C21 SOIC EEPROM ST
74HC4052 SOP 4-Channel Analog DE/Multiplexer PHILIPS
BA7657F SOP Switch ic ROHM
74ACT244 TSSOP Octal Buffer and Line Driver FAIRCHILD
PCF8563T SOP CMOS Real-time Clock PHILIPS
K4S643232f TSOP DRAM Samsung Elec.
K6T4016V3C TSOP SRAM Samsung Elec.
TEA6425D SO20L Video Cellular Matrix ST
KIA78D09F DPAK Regulator KEC
RM1A-A BGA-352 scaler OPLUS
PCF8574T SOT162 Remote 8-bit I/O Expander PHILIPS
TA2024 PSOP30 Digital Audio Amplifier Driver TRIPATH
TL062CDT SO8 J-FET Dual Operational Amplifiers ST
MSP3450G PQFP80 Multistandard sound processor family MICRONAS
Three-dimensional Y/C separation lsi with on-chip memory NEC
1) upd64083 realizes a high precision Y/C separation
2) noise reduction by three-dimension signal processing for NTSC signal
3) on-chip 4-Mbit memory for flame delay,2ch of high precision intermal
UPD64083GF QFP100
10-bit A/D converter, and adapting 10-bit signal processing and high
picture quality
4) upd64083 is completely single-chip system of 3D Y/C separation
5) This LSI includes the wide
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6. IC layout &power map 6.1 IC layout & power map(digital board)
31P CON. 11P CON.
74VHC 74VHC D3.3V
02 02 STB5V D3.3V A6V
STB3.3V K4S K4S K4S DS90C385 LP 78D LM
Z86129
643232F 643232F 643232F D2.5V 9361 05F 2937
14 74AHC 74AHC 2.5 3,3 12
P 244 244 D2.5V LM A5V A5V P
C 1086 STB5V C
O IS-3.3 O
N. N.
STB3.3V STB3.3V D3.3V
K6T4016V3C LP 74ACT 74ACT
MAX RAMBRANT-1A 9361 244 244
821 D1.8V 1.8 74ACT VPC 12
STB3.3V 244 74ACT 74ACT P
STB5V D3.3V D3.3V D3.3V 244 244 3230 C
O
N.
74ACT
R8820LV STB5V 244
STB5V FLI2200
A5V 74ACT D2.5V 12
A5V 244 P
24C16 D3.3V LM C
1086 O
D3.3V 74LCX7 N.
74ACT 74VHC 4 IS-3.3
M29W160DB 244 08
K4S643232F D3.3V 12
AD9887KS ADG774 P
C
-140 O
PCF VPC N.
8563T
74HC 3230
A3.3V A3.3V STB5V 4052
74HC
LM 4FC 24C16 LM 4FC 4052
MAX 2937 216 2937 216
2323E 3,3 3,3 A5V A5V
STB5V
STB5V S-
A5V Video
PC
RS232I
RS232 OUT N DVI Audio_PC/DVI_LR Audio_SVideo_LR Audio_Video_LR
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6.2 IC layout & power map(analog board)
10P CON.
A33V
12Vamp LM
78D 78D A9V 2940
A6V 05F 09F IMP8
12 3,3 A9V
P LP
C A12V A5V 2961 A5V A5V
O
A2.5V 2.5V
N. MSP
LM
UPD A3.3V 2937
3450G
12 3.3V A33V
P 64083 3,3
C A5V
O TCPS9091PD27A
N.
LP 12Vamp TL062
A2.5V 2961 CDT
12 2.5V
P
C
O
N.
TEA PCF PCF
LM A8V 6425D 8574T 8591T 12Vamp TA2024
2940
12 IMP8
P 3,3
C
O
N. BA7657F BA7657F
A5V
A5V
RF
VIDEO DTV Audio_DTV_LR DVD Audio_DVD_LR Audio_OUT_LR Woofer
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7.Panel interface
7.1 Output signal timing_60HZ
SIGNAL TIMING SIGNAL TIMING
Dot Clock 27 M HZ
H-Frequency 31.05HZ V-Frequency 59.99 HZ
H-Total 896 dots V-Total 533 H
H-Front Porch 16 dots V-Front Porch 12 H
H-Sync 12 dots V-Sync 2H
H-Back Porch 16 dots V-Back Porch 29 H
H-Active 852 dots V-Active 480 H
H-Sync Polarity P V-Sync Polarity P
7.2 Output signal timing_50HZ
SIGNAL TIMING SIGNAL TIMING
Dot Clock 27 M HZ
H-Frequency 31.05HZ V-Frequency 50 HZ
H-Total 896 dots V-Total 639 H
H-Front Porch 10 dots V-Front Porch 12 H
H-Sync 24 dots V-Sync 2H
H-Back Porch 10 dots V-Back Porch 135 H
H-Active 852 dots V-Active 480 H
H-Sync Polarity P V-Sync Polarity P
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7.3 Output signal timing diagram
HORIZONTAL TIMING DIAGRAM
12 D 16D 852D 16D
896D
VERTICAL TIMING DIAGRAM
2H 12H 480H 29H(135H)
533H(639H)
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7.4 LVDS bit mapping
Pin Name signal Pin Name signal Pin Name signal Pin Name signal
TXIN0 R0 TXIN7 G0 TXIN14 G5 TXIN21 B4
TXIN1 R1 TXIN8 G1 TXIN15 B0 TXIN22 B5
TXIN2 R2 TXIN9 G2 TXIN16 B6 TXIN23 FIELD
TXIN3 R3 TXIN10 G6 TXIN17 B7 TXIN24 HSYNC
TXIN4 R4 TXIN11 G7 TXIN18 B1 TXIN25 VSYNC
TXIN5 R7 TXIN12 G3 TXIN19 B2 TXIN26 ENABLE
TXIN6 R5 TXIN13 G4 TXIN20 B3 TXIN27 R6
7.5 Panel connect pin configuration
PIN NO. signal PIN NO. signal PIN NO. signal PIN NO. signal
1 GND 9 GND 17 GND 25 N.C.
2 GND 10 GND 18 GND 26 GND
3 Txout0- 11 Txout2- 19 Txout3- 27 N.C.
4 Txout0+ 12 Txout2+ 20 Txout3+ 28 GND
5 Gnd 13 GND 21 GND 29 N.C.
6 Gnd 14 GND 22 GND 30 GND
7 Txout1- 15 TxCLKout0- 23 GND 31 N.C.
8 Txout1+ 16 TxCLKout0+ 24 GND
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8.Power interface
DIGITAL BOARD ANALOG BOARD
PIN
NUMBER
INPUT POWER(CN6001) INPUT POWER(CN1000)
1 A5V A6V
2 GND GND
3 D3.3V A12V
4 D3.3V GND
5 GND 12VAMP
6 GND 12VAMP
7 NC GND
8 POWER-N GND
9 GND A33V
10 STB5V GND
11 THER_DET
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9.Inspections on major ICs
9.1R8820LV(DIGITAL:U9102)-MICOM
(1)Check whether the proper power is supplied(3.3v)
(2)Check whether the No.71 Reset pin's output is high.
(3)Check I2C-BUS (I2C :PINS 76 and 77)
(4)Check whether the inputs/outputs betwenR8820LV and MEMORY(U9101,U9103) are normal.
(5)Check whethet the 25MHZ clock is connected to pins 13 and 14.
9.2VPC3230(digital:U9513)_Check when the input mode is set for TV,VIDEO,S-VIDEO,DVD
(1) Check whether the proper power is supplied.(5v,3.3v)
(2) Check whether the No.15 Reset pin's output is high.
(3) Check the I2C-bus(pin 13 and 14).
(4) Check whethet the output clock of llc1(pin 28) is 13.5M HZ.
(5) Check the output on VPC_h sync(pin56),VPC_VYNC(PIN57),VPC_FIELD(PIN53).
(6) Check whethet the 20.25Mhz clock is connected to pins 62 and 63.
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(7) Check the digital data outputs.
9.3 TEA6425D(ANALOG:U1002)
-VIDEO Switching IC_Check when the input mode is set for TV,VIDEO,S-VIDEO
(1) Check whether the proper power is supplied.(8v)
(2) Check the I2C bus (pin2 and pin4).
(3) Check whether the inputs/outputs are normal.
9.4 MDIN-150(digital :U9507)
-DEINTERLACE_Check when the input mode is for TV,VIDEO ,S-VIDEO,DVD.
(1) Check whether the proper power is supplied(3.3v,2.5v)
(2) Check whether the NO.209 Reset pin's output is high.
(3) Check the I2C-bus (pins 62 and 64).
(4) Check whether the 27Mhz clock is connected to pins 186 and 187.
(5) Check whether the data inputs are normal.
VPC-CLK(pin 195):13.5MHZ,VPC_HSYNC(pin 189):15.75Khz,
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VPC_VSYNC(pin 188):60HZ,VPC_FIELD(pin 194)
(6) Check whether the data outputs are normal.
V_CLK(pin159):27MHZ,V_HYNC(pin 165):31.5Khz,V_VSYNC(pin 168):60HZ,V_ACTIVE (pin
164),D_V_VALID(pin163)
(7) Check whether the inputs and outputs between MDIN-150 and MEMORY (U9501) are normal.
9.5 TCP9091PD27A(ANALOG:U1001)_Check when the input mode is set for TV
(1) Check whether the proper power is supplied .(33V,5V)
(2) Check the I2C bus (pin 2 and 4).
(3) Check whether the inputs/outputs are normal.
9.6 AD9887AKS(digital:U9201)-A/D CONVERTER_Check when the input mode is DTV,PC,DVI.
(1) Check whether the proper power is supplied(3.3V)
(2) Check I2C bus (pins 91 and 92).
(3) Check whether the inputs/outputs are normal.
INPUT:
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PC INPUT:pin119