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ZZZ2 ZZZ1 ZZZ3 ZZZ4 11/18
LA-7072P P/N from DA60000LA00 to DA60000LA10
LS-7072P P/N from DA40000Z300 to DA40000Z310
LS-7073P P/N from DA40000Z400 to DA40000Z410
PCB LA-7072P LS-7072P LS-7073P
M/B M/B LED/B TP/B
DAZ@ DA@ DA@ DA@ 11/22
LS-7073P P/N from DA40000Z410 to DA20000Z410
1
11/18 ZZZ2 for DAZ P/N:DAZ0IV00101 1
Compal Confidential
2
P0VE6 LA7072P Schematics Document 2
AMD Ontario Processor with DDRIII + Hudson M1
10.1" M/B
3
2010-11-18 3
Rev : 1.0
[email protected]
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P0VE6 Schematics
Date: Monday, November 22, 2010 Sheet 1 of 36
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A B C D E
Compal Confidential
Model Name : P0VE6 / P0VH6 Brazos Platform
File Name : LA-7072P
HDMI
1 AMD Memory Bus (DDRIII) 1
RGB
Single Channel 204 Pin DDRIII SO-DIMM x1
LVDS Ontario FT1
APU 1.5V DDRIII 800/1066 BANK 0, 1, 2, 3
6.4G/8.5G
BGA 413-Ball Page 7
100M/133M
19mm X 19mm
Page 4,5,6
HDMI Conn. D-Sub Conn. LVDS Conn. UMI x4
Page 9 Page 10 Page 8
Gen.1 USB Conn.x1 USB Conn.x2 Camera Bluetooth Card Reader
(Right Side) (Left Side) ENE 6250 / 6252
2.5GT/s Port 5 Port 7
Port 2 Port 0, 1 Port 6
per Lane Page 24 Page 24 Page 8 Page 19 Page 18
2
Fan Circuit 2
PWM Page 26 USB 3.3V 48MHz
PCI-Express X3 AMD
Hudson M1 HD Audio 3.3V 24MHz
100MHz PCIE Gen1 2.5GT/S FCH SATA 3G Card
Gen1 1.5GT/S ,Gen2 3GT/S 100MHz
Port 1 Port 3 Port 2 BGA 605-Ball Port 3
23mm X 23mm Page 19
WWAN WLAN LAN(10/100mbE) Page 11,12,13,14,15
JMINI1 JMINI2
AR8152
Media processor Wireless Card HDD
Port 1 Port 3 Port 2
Page 19 Page 20 Page 17
(2.5")
LPC Port 0
Page 21
33MHz
3 3
RJ-45
Page 17
HDA Codec+AMP
ENE KB930 CX20584
Page 25 Small Board Page 16
LED/B TP BTN/B
LS-7072P LS-7073P HP Jack x1
MIC Jack x1
Page 23
RTC Ckt.
Page 11
BIOS ROM
4 2MB 4
Power Button Page 26
Page 22
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/12 2012/08/12 Title
DC/DC Interface Ckt. Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Page 27 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P0VE6 Schematics
Date: Monday, November 15, 2010 Sheet 2 of 36
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A B C D E
Voltage Rails FCH Hudson-M1 Brazos FCH Hudson-M1
Power Plane Description S1 S3 S5 USB Port List PCIE Port List SATA Port List
VIN Adapter power supply (19V) N/A N/A N/A USB1.1 PCIE0 SATA0 HDD
B+ AC or battery power rail for power circuit. N/A N/A N/A
Port0 NC PCIE1 SATA1 NC
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
NC
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 SATA2 NC
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
+0.75VS 0.75VS switched power rail for DDR terminator
USB2.0 PCIE3 SATA3 NC
ON OFF OFF
+1.05VS 1.05V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Right USB2 PCIE0 NC SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 Right USB3 PCIE1 WWAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Left USB1 PCIE2 LAN
+1.1VALW 1.1V always on power rail ON ON ON*
Port3 WWAN PCIE3 WLAN
+3VS 3.3V switched power rail ON OFF OFF
+1.5VS 1.5VS switched power rail ON OFF OFF Port4 SIM
+5VALW 5V always on power rail ON ON ON*
Port5 USB Camera
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON* Port6 CardReader
+RTCBATT RTC power ON ON ON
Port7 BT
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port8 WiMax
2 Port9 NC 2
EC SM Bus1 address EC SM Bus2 address
Port10 NC
Device Address HEX Device Address HEX
Smart Battery 0001-011xb 16H SB-TSI 1001-100xb 98H
Port11 NC
Port12 NC
Port13 NC
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Board ID / SKU ID Table for AD channel
Vcc +3VALW
Device Address HEX
Ra 100K +/- 5%
APU SIC/SID (FCH_SMB3) Board ID Rb V AD_BID min V AD_BID typ V AD_BID max PCB Revision
H_THERMTRIP# (FCH_ALERT#) 0 0 0 V 0 V 0 V
* 0.1
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 0.2
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
3
SM Bus Controller 1 (FCH_SMB0) 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 3
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
Device Address HEX
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 7 NC 2.500 V 3.300 V 3.300 V
SMBUS Control Table
BOM Structure Source BATT DIMM MINI Card LCD DDC ROM HDMI DDC ROM APU
EC_SMB_CK1 KB930
EC_SMB_DA1 V
HDMI@ : HDMI function
EC_SMB_CK2 KB930
BT@ : BT function EC_SMB_DA2 V
CONN@ : Connetors
HDMI_DATA APU FT1
45@ : 45 Level HDMI_CLK V
3G@ : 3G function
EDID_DATA APU FT1
3G_MP@: 3G & Media processor function EDID_CLK V
[email protected]
4 4
CHARGE@: Charge BATT
FCH_SMDAT0 FCH M1
NONCHARGE@: nonCharge BATT FCH_SMCLK0 V V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/12 Deciphered Date 2012/08/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P0VE6 Schematics
Date: Monday, November 15, 2010 Sheet 3 of 36
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5 4 3 2 1
U1 10/08 Add U1(C50@) SA00004BM30 S IC ONTARIO ZM101034B2238 1G BGA ABO!
R9 R352 Display
10/08 Change U1 P/N to SA00004DF20 S IC ONTARIO ZM121034B1238 1.2G BGA ABO!
10/27 APU P/N update to B0 stepping mount @ LVDS
S IC ONTARIO ZMC50AFPB22GT 1G BGA 413P ABO !
SA00004DF60 *
11/03 APU P/N update to SA00004DF60(C30) SA00004BM80(C50) U1B @ mount eDP
+1.8VS SA00004KD40 HDMI_TX2P_C DP_ZVSS
C1 .1U_0402_16V7K R1 2 150_0402_1%
DISPLAYPORT 1
<9> HDMI_TX2P 1 2 A8 TDP1_TXP0 DP_ZVSS H3 1
C50@ C6 .1U_0402_16V7K HDMI_TX2N_C
DP MISC
<9> HDMI_TX2N 1 2 B8
TDP1_TXN0
DP_BLON G2 APU_ENBKL <25>
C2 1 2 .1U_0402_16V7K HDMI_TX1P_C B9 H2
<9> HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD <8>
C3 1 2 .1U_0402_16V7K HDMI_TX1N_C A9 H1
D APU_SVC <9> HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM <8> D
R3 1 2 1K_0402_5%
R4 1 2 1K_0402_5% APU_SVD C7 1 2 .1U_0402_16V7K HDMI_TX0P_C D10
<9> HDMI_TX0P HDMI_TX0N_C TDP1_TXP2 HDMI_CLK
C8 1 2 .1U_0402_16V7K C10 B2
<9> HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK <9>
C2 HDMI_DATA HDMI_DATA <9>
R8 TEST_25_L HDMI_CLKP_C TDP1_AUXN
1 2 510_0402_1% <9> HDMI_CLKP
C4 1 2 .1U_0402_16V7K A10 8/25 Pull-up 100k(@ R352) to +3VS
R6 TEST36 HDMI_CLKN_C TDP1_TXP3
1 2 1K_0402_5% <9> HDMI_CLKN
C5 1 2 .1U_0402_16V7K B10 C1 HDMI_DET <9>
TDP1_TXN3 TDP1_HPD on LTDP0_HPD for eDP
11/29 Change U1 from SA00004BM80 to SA00004KD40 B5 A3 EDID_CLK EDID_CLK <8>
<8> LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_DATA
DISPLAYPORT 0
<8> LVDS_A2# A5 LTDP0_TXN0 LTDP0_AUXN B3 EDID_DATA <8>
R352 1 @ 2 100K_0402_5% +3VS
+3VS D6 D3 LTDP0_HPD R9 1 2 100K_0402_5%
<8> LVDS_A1 LTDP0_TXP1 LTDP0_HPD
<8> LVDS_A1# C6
R10 10K_0402_5% HDMI_DATA LTDP0_TXN1
1 2 DAC_RED C12 DAC_RED <10>
R11 1 2 10K_0402_5% HDMI_CLK A6 D13 R12 1 2 150_0402_1%
APU_PROCHOT# <8> LVDS_A0 LTDP0_TXP2 DAC_REDB
R13 1 2 1K_0402_5% B6 A12
<8> LVDS_A0# LTDP0_TXN2 DAC_GREEN DAC_GRN <10>
R14 1 2 1K_0402_5% APU_ALERT#_R B12 R15 1 2 150_0402_1%
R16 1K_0402_5% APU_SIC DAC_GREENB
1 2 D8 A13
VGA DAC
APU_SID <8> LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU <10>
R17 1 2 1K_0402_5% C8 B13 R18 1 2 150_0402_1%
<8> LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
<11> APU_CLK V2 E1 CRT_HSYNC <10>
CLKIN_H DAC_HSYNC
<11> APU_CLK# V1 E2 CRT_VSYNC <10>
CLKIN_L DAC_VSYNC
CLK
<11> DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <10>
<11> DISP_CLK# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <10>
C405 1 2 100P_0402_50V8J LDT_RST# J1 D12 DAC_ZVSS R19 1 2 499_0402_1%
<35> APU_SVC SVC DAC_ZVSS
Power Circuit <35> APU_SVD
J2
SVD
SER
10/05 Add 100p(C405) on LDT_RST# APU_SIC TEST4
R1
APU_SID
P3 SIC TEST5 R2 PAD T2 10/01 Remove T1,T3~T7,T11,T12,T31,T32
9/9 Change R24 from @ to mount R26 from mount to @ P4 SID TEST6 R6
T5
TEST14 TEST15 R20
9/15 Change R24 from mount to @ <11> LDT_RST# T3 E4 1 2 1K_0402_5%
C RESET_L TEST15 C
<11> APU_PWRGD T4 K4
CTRL
PWROK TEST16
L1
APU_PROCHOT# TEST17 TEST18 R21
U1 L2 1 2 1K_0402_5%
APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19 R22
M2 1 2 1K_0402_5%
TEST
THERMTRIP_L TEST19
R23 1 @ 2 0_0402_5% APU_PROCHOT# <13> APU_ALERT#_FCH
R24 1 @ 2 0_0402_5% APU_ALERT#_R T2
ALERT_L TEST25_H K1 TEST25_H R25 1 2 510_0402_1%
<11> FCH_PROCHOT# R26 1 @ TEST_25_L
<25> APU_ALERT#_EC 2 0_0402_5% K2
R27 APU_TDI TEST25_L
1 2 0_0402_5% N2 TDI TEST28_H L5
<25> EC_PROCHOT# APU_TDO
Connection to EC, FCH input need to pull-down N1
TDO TEST28_L
M5
APU_TCK P1 M21 TEST31 PAD T8
TCK TEST31
JTAG
APU_TMS P2 J18 TEST33_H C9 1 2 0.1U_0402_16V4Z R28 1 2 51_0402_1%
APU_TRST# TMS TEST33_H TEST33_L C10 1
T9 PAD M4 TRST_L TEST33_L J19 2 0.1U_0402_16V4Z R29 1 2 51_0402_1%
APU_DBRDY M3 U15
T10PAD DBRDY TEST34_H
Close to APU APU_DBREQ# M1