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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
CONTENTS 1 1.1 1.2 2 2.1 3 4 5 6 7 7.1 8 8.1 8.1.1 8.1.2 8.1.3 9 9.1 9.1.1 9.1.2 9.2 9.3 10 11 12 12.1 12.2 12.3 12.4 12.4.1 12.4.2 12.5 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.7 12.7.1 12.7.2 12.8 12.8.1 12.8.2 12.9 13 FEATURES PCF84CXXXA kernel Derivative features PCA84C640 GENERAL DESCRIPTION Important ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION DIFFERENCES RESET Power-on-reset ANALOG CONTROL 6-bit PWM DACs Pin selection for PWM outputs Polarity of the PWM outputs Analog output voltage VST CONTROL 14-bit PWM DAC 14-bit counter Data and interface latches Coarse adjustment Fine adjustment AFC INPUT INPUT/OUTPUT ( I/O) ON SCREEN DISPLAY Features Horizontal display position control Vertical display position control Clock generator RC oscillator LC oscillator Display data registers Display control registers Derivative register OSDCA Derivative registers LINE 0A and LINE 0B Derivative registers LINE 1A and LINE 1B Derivative register OSDCB OSD display position Vertical position Horizontal position OSD character size and colour selection Character size Colour selection Character ROM EMULATION MODE 14 15 16 17 17.1 18 19 19.1 19.1.1 19.1.2 20 21 22
84C44X; 84C64X; 84C84X
REGISTER MAP LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS Characteristic curves PACKAGE OUTLINE SOLDERING Plastic dual in-line packages By dip or wave Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
October 1994
2
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
1 1.1 FEATURES PCF84CXXXA kernel
84C44X; 84C64X; 84C84X
· Four programmable display dot sizes · Half dot character rounding · Seven colours for each character · One 14-bit PWM output for VST · Five 6-bit PWM outputs for analog controls · Eight port lines with 10 mA LED drive capability · 18 general purpose bidirectional I/O lines plus 11 function-combined I/O lines · 2 direct testable lines · Programmable VSYNCN and HSYNCN input polarity · RC oscillator for OSD function. 2 GENERAL DESCRIPTION
· 8-bit CPU, ROM, RAM, I/O in a single 42 leads shrink DIL package · Over 80 instructions all of 1 or 2 cycles · 29 quasi bidirectional standard I/O port lines · Configuration of I/O lines individually selected by mask · External interrupt INT/T0 · 2 direct testable inputs T0, T1 · 8-bit programmable timer/event counter · 3 single level vectored interrupts (external, timer/counter, I2C-bus) · Power-on-reset and low voltage detector · Single power supply · 2 power reduction modes: Idle and Stop · Operating temperature range: -20 to +70 °C · Silicon gate CMOS fabrication process (SAC2). 1.2 Derivative features PCA84C640
The 84C44X; 84C64X; 84C84X denotes the types: · PCA84C440; 84C441; 84C443; 84C444 · PCA84C640; 84C641; 84C643; 84C644 · PCA84C840; 84C841; 84C843; 84C844, which are 8-bit microcontrollers with On Screen Display (OSD) and Voltage Synthesized Tuning (VST) functions. All are members of the 84CXXX microcontroller family. There are two oscillator types for the OSD function in the various types, i.e., · RC oscillator: PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843 · LC oscillator: PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844. 2.1 Important note
Although the PCA84C640 is specifically referred to throughout this data sheet, the information applies to all the devices. The small differences between the 84C640 and the other devices are specified in the text and also highlighted in Chapter 6. The PCA84C640 comprises: · The PCF84CXXXA processor core · 6 kbytes mask-programmable program ROM · 128 bytes RAM · Multi-master I2C-bus interface · AFC input for Voltage Synthesized Tuning (VST; with 3-bit DAC and comparator) · On Screen Display (OSD) facility for two rows of 16-characters · On Screen Display character set of 64 types 3 ORDERING INFORMATION
This data sheet details the specific properties of the PCA84C44X, PCA84C64X and PCA84C84X. The shared characteristics of the PCA84CXXX family of microcontrollers are described in the PCF84CXXXA Family single-chip 8-bit Microcontroller of "Data Handbook IC14", which should be read in conjunction with this data sheet.
PACKAGE TYPE NUMBER NAME PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843 PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844 DESCRIPTION VERSION
TEMPERATURE RANGE (°C)
SDIP42
plastic shrink dual in-line SOT270-1 package; 42 leads (600 mil)
-20 to +70
October 1994
3
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
4 BLOCK DIAGRAM
84C44X; 84C64X; 84C84X
handbook, full pagewidth
T1 (6)
INT / T0
VOB
VOW2
DOSC1
VSYNCN
VOW1
VOW3
DOSC2 HSYNCN (3)
XTAL1 (IN) 8-BIT TIMER / EVENT COUNTER ROM (1) RAM (2) DISPLAY ON SCREEN
CPU
XTAL2 (OUT)
8-bit internal bus
RESET PARALLEL I/O PORTS 84CXXX core excluding ROM / RAM 8-BIT I/O PORTS
TEST / EMU
6-BIT DAC
14-BIT DAC
3-BIT DAC + COMPARATOR
I2 C INTERFACE
8
5
8
8
MCD170
P0
P1
DP0 DP1 (5)
1 2 3 4 5 PWM
TDAC
AFC
SDA (4)
SCL
(1) 4K bytes for the PCA84C440; 84C441; 84C443; 84C444. 6K bytes for the PCA84C640; 84C641; 84C643; 84C644. 8K bytes for the PCA84C840; 84C841; 84C843; 84C844. (2) 128 bytes for the PCA84C440; 84C441; 84C443; 84C444; 84C640; 84C641; 84C643; 84C644. 192 bytes for the PCA84C840; 84C841; 84C843; 84C844. (3) For use with an LC oscillator, only available with the: PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844. (4) I2C-bus interface not available with the: PCA84C443; 84C444; 84C643; 84C644; 84C843; 84C844. (5) DP1.4 only available for PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843. (6) T1 = pin 29 for PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843. T1 = pin 34 for PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844.
Fig.1 Block diagram.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
5 PINNING INFORMATION
84C44X; 84C64X; 84C84X
handbook, halfpage
DP0.0/TDAC DP0.1/PWM1 DP0.2/PWM2 DP0.3/PWM3 DP0.4/PWM4 DP0.5/PWM5 P1.0 P1.1 DP1.7/AFC
1 2 3 4 5 6 7 8 9 PCA84C440 PCA84C443 PCA84C640 PCA84C643 PCA84C840 PCA84C843
42 VDD 41 DP1.0 40 DP0.6/SDA 39 DP0.7/SCL 38 DP1.1 37 DP1.2 36 DP1.3 35 INT / T0 34 DP1.4 33 RESET 32 XTAL2 31 XTAL1 30 TEST/EMU 29 T1 28 DOSC1 27 VSYNCN 26 HSYNCN 25 VOB 24 VOW3 23 VOW2/DP1.5 22 VOW1/DP1.6
MCD172
handbook, halfpage
DP0.0/TDAC
1 2 3 4 5 6 7 8 9 PCA84C441 PCA84C444 PCA84C641 PCA84C644 PCA84C841 PCA84C844
42 VDD 41 DP1.0 40 DP0.6/SDA 39 DP0.7/SCL 38 DP1.1 37 DP1.2 36 DP1.3 35 INT/T0 34 T1 33 RESET 32 XTAL2 31 XTAL1 30 TEST/EMU 29 DOSC2 28 DOSC1 27 VSYNCN 26 HSYNCN 25 VOB 24 VOW3 23 VOW2/DP1.5 22 VOW1/DP1.6
MCD171
DP0.1/PWM1 DP0.2/PWM2 DP0.3/PWM3 DP0.4/PWM4 DP0.5/PWM5 P1.0 P1.1 DP1.7/AFC
P1.2 10 P1.3 11 P1.4 12 P0.0 13 P0.1 14 P0.2 15 P0.3 16 P0.4 17 P0.5 18 P0.6 19 P0.7 20 VSS 21
P1.2 10 P1.3 11 P1.4 12 P0.0 13 P0.1 14 P0.2 15 P0.3 16 P0.4 17 P0.5 18 P0.6 19 P0.7 20 VSS 21
Fig.2 Pinning diagram for PCA84CX40; 84CX43.
Fig.3 Pinning diagram for PCA84CX41; 84CX44. 5
October 1994
Table 1 PIN(1) DESCRIPTION
Pin description
SYMBOL(1)
October 1994 41, 38, 37, 36, 34 41, 38, 37, 36 29 28 - 28, 29 Connections to LC oscillator of OSD clock. - Connection to RC oscillator of OSD clock. 34 Direct testable pin and event counter input. Derivative Port 1: quasi-bidirectional I/O lines. 1 2 to 6 7, 8, 10, 12 13 to 20 9 40 39 35 23, 22 33 32, 31 30 27 26 25 24 21 42 Initialize input, active LOW. Oscillator output or input terminal for system clock. Control input for testing and emulation mode. Ground for normal operation. Vertical synchronous signal input. Horizontal synchronous signal input. Blanking output. Character video output of OSD. Ground. Power supply. External interrupt or direct testable line. Derivative Port 1: quasi-bidirectional I/O lines or character video output. Port 0: quasi-bidirectional I/O port. Derivative Port 1: quasi-bidirectional I/O line or comparator input with 3-bit DAC. Derivative open drain I/O port or I2C-bus data line. Derivative open drain I/O port or I2C- bus clock line. Port 1: quasi-bidirectional I/O lines. Derivative Port 0: quasi-bidirectional I/O line or 14-bit DAC PWM. Derivative Port 1: quasi-bidirectional I/O lines or 6-bit DAC PWM.
84CX40; 84CX43 84CX41; 84CX44 84CX40; 84CX43 84CX41; 84CX44
Deviating pinning
DP1.0 to DP1.4
DP1.0 to DP1.3
Philips Semiconductors
T1
T1
DOSC1
-
-
DOSC1/DOSC2
Mutual pinning
DP0.0/TDAC
DP0.1 to DP0.5/PWM1 to PWM5
P1.0 to P1.4
P0.0 to P0.7
DP1.7/AFC
DP0.6/SDA
8-bit microcontrollers with OSD and VST
6
DP0.7/SCL
INT/T0
DP1.5 to DP1.6/VOW2 to VOW1
RESET
XTAL2, XTAL1
TEST/EMU
VSYNCN
HSYNCN
VOB
VOW3
VSS
VDD
84C44X; 84C64X; 84C84X
Note
Product specification
1. 84CX40; 84CX43 denotes the types: PCA84C440, PCA84C443, PCA84C640, PCA84C643, PCA84C840 and PCA84C843. 84CX41; 84CX44 denotes the types: PCA84C441, PCA84C444, PCA84C641, PCA84C644, PCA84C841 and PCA84C844.
6
Table 2 Differences between the types PCA84C44X, PCA84C64X and PCA84C84X In this table: yes = available; no = not available. PCA...
October 1994 LC 17 yes 4 kbytes 128 bytes 128 bytes 192 bytes 6 kbytes 8 kbytes no no yes yes no no yes yes no no 18 17 18 17 18 17 18 17 18 17 RC LC RC LC RC LC RC LC RC LC DOSC2 T1 DP1.4 T1 T1 DOSC2 T1 DOSC2 T1 DOSC2 T1 T1 DOSC2 DP1.4 T1 DP1.4 T1 DP1.4 T1 DP1.4 T1 DOSC2 DIFFERENCES BETWEEN THE TYPES no no yes no yes no yes no yes no yes no yes no yes no yes no yes yes no no
FEATURE
84C440 84C441 84C443 84C444 84C640 84C641 84C643 84C644 84C840 84C841 84C843 84C844
OSD oscillator
RC
Philips Semiconductors
General purpose I/O lines 18
I2C-bus interface
yes
ROM
RAM
Pin assignment
Pin 29
T1
Pin 34
DP1.4
Register DP1 (bit DP1.4)
Pin
yes
Latch
yes
8-bit microcontrollers with OSD and VST
7
84C44X; 84C64X; 84C84X
Product specification
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
7 RESET 7.1
84C44X; 84C64X; 84C84X
Power-on-reset
The RESET pin (active LOW input) is used to initialize the microcontroller to a defined state. The Reset configuration is shown in Fig.5.
The Power-on-reset circuit monitors the voltage level of VDD. If VDD remains below the internal reference voltage level Vref (typically 1.3 V), the oscillator is inhibited. When VDD rises above Vref, the oscillator is released and the internal reset is active for a period of td (typically 50 µs). Considering the VDD rise time, the following measures for a correct Power-on-reset can be taken: · If the VDD rises above the minimum operation voltage before time period td is exceeded, no external components are necessary (see Fig.6). · If VDD has a slow rise time, such that after the time period (t Vref + t d ) has elapsed the supply voltage is still
handbook, halfpage
VDD R 100 k
RESET
C
MCD174
VSS
below the minimum operation voltage (Vmin), external components are required (see Figs 4 and 7). To guarantee a correct reset operation, ensure that the time constant RC 8 × t VDD . A definite Power-on-reset can be realized by applying an (external) RESET signal during power-on.
Fig.4 External components for RESET pin.
handbook, full pagewidth
oscillator inhibit
VDD
Vref
POWER ON RESET RESET
internal reset
V SS
MLA651
Fig.5 Reset configuration.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, full pagewidth
VDD V ref VSS
VDD
VDD RESET VSS td
OSCILLATOR
oscillator start up time
MCD240
Fig.6 Reset with fast rising VDD.
handbook, full pagewidth
VDD
VDD Vmin Vref VSS t VDD
RESET
without external component
VDD
VSS t Vref td
RESET
with external component
VDD
VSS RC 8 t VDD
OSCILLATOR
oscillator start up time
MCD241
Fig.7 Reset with slow VDD. October 1994 9
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
8 8.1 ANALOG CONTROL 6-bit PWM DACs 8.1.3
84C44X; 84C64X; 84C84X
ANALOG OUTPUT VOLTAGE
Five PWM outputs are available for analog control purposes e.g. volume, balance, brightness, saturation etc. The block diagram of a typical 6-bit PWM DAC is shown in Fig.8. Each PWM output can generate pulses of programmable length that have a repetition frequency of 1/ × f 1 64 PWM, where fPWM = /3 × fXTAL. 8.1.1 PIN SELECTION FOR PWM OUTPUTS
A DC voltage proportional to the PWM control setting may be obtained by connecting an integrating network to each of the PWM outputs (see Fig.9). The analog value is calculated as follows: t HIGH V A = ------------- × V O tr Where: · t HIGH = t 0 × PWMDL = HIGH time of the PWM pulse · t r = t 0 × 64 = repetition time of the PWM pulse 3 · t 0 = ------------f XTAL · PWMDL is the decimal value of the contents of the PWM data latch. Therefore, the analog output voltage is: PWMDL V A = ----------------------- × V O 64
The PWM outputs PWM1 to PWM5, share the same pins as the Derivative Port lines DP0.1 to DP0.5. Setting the (relevant PWM enable) bit PWMnE to: · Logic 1, selects the relevant PWMx output function · Logic 0, selects the relevant DP0.x Port function. 8.1.2 POLARITY OF THE PWM OUTPUTS
The polarity of all five PWM outputs is selected by the state of the polarity control bit P6LVL. Setting the control bit P6LVL to: · Logic 0, sets the PWMx outputs to the default polarity · Logic 1, inverts all the PWMx outputs.
handbook, full pagewidth
f PWM
6-BIT PWM DATA LATCH
DP0.x data I/O
PWMnE
6-BIT DAC PWM CONTROLLER
Q Q DP0.x / PWMx
P6LVL
polarity control bit
MCD176
Fig.8 Block diagram of the 6-bit PWM DAC.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, full pagewidth
t0
f PWM 64 1 2 3 m m+1 m+2 63 64 1
00
01
m
63
decimal value PWM data latch
MCD175
Fig.9 PWM output patterns (P6LVL = 0).
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
9 9.1 VST CONTROL 14-bit PWM DAC 9.2
84C44X; 84C64X; 84C84X
Coarse adjustment
The PCA84C640 has one 14-bit PWM DAC output (TDAC) with a resolution of 16384 levels for Voltage Synthesized Tuning. The PWM DAC (see Fig.10) consists of: · 14-bit counter · Two 7-bit DAC interface data latches (VSTH and VSTL) · One 14-bit DAC data latch (VSTREG) · Pulse control. The polarity of output TDAC is selected with bit P14LVL. Setting the bit P14LVL to: · Logic 1, sets the TDAC output to the default polarity · Logic 0, inverts the TDAC output. 9.1.1 14-BIT COUNTER
The coarse adjustment output (OUT1) is reset to LOW (inactive) at the start of each tsub period. It will remain LOW until the time [ t 0 × ( VSTH + 1 ) ] has elapsed and then will go HIGH and remain so until the next tsub period starts. 9.3 Fine adjustment
Fine adjustment is achieved by generating additional pulses at the start of particular sub-periods (tsubn). These additional pulses have a width of t0. The sub-period in which a pulse is added is determined by the contents of VSTL interface latch. Table 3 gives the numbers of the tsubn, at the start of which an additional pulse is generated, depending on the bit in VSTL being a logic 0. When more than one bit is a logic 0 a combination of additional pulses are generated. For example, if VSTL = 1111010, which is a combination of · VSTL = 1111110: sub-period 64, and · VSTL = 1111011: sub-periods 16, 48, 80, 112, then additional pulses will be given in sub-periods 16, 48, 64, 80 and 112; this is illustrated in Fig.12. If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0, then the TDAC output is as shown in Fig.13. Table 3 Additional pulse distribution ADDITIONAL PULSE IN SUB-PERIODS tsubn 64 32, 96 16, 48, 80, 112 8, 24, 40, 56, 72, 88, 104, 120 4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124 2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126 1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127
The counter is continuously running and is clocked by f0. 3 The period of the clock, t 0 = ------------f XTAL The repetition time for one complete cycle of the counter: t r = t 0 × 16 384 The repetition time for one cycle of the lower 7-bits of the counter is: t sub = t 0 × 128 Therefore, the number of tsub periods in a complete cycle tr is: t 0 × 16 384 N = --------------------------- = 128 t 0 × 128 9.1.2 DATA AND INTERFACE LATCHES
LOWER 7 BITS (VSTL) 111 1110 111 1101 111 1011 111 0111 110 1111 101 1111 011 1111
In order to ensure correct operation, interface data latch VSTH is loaded first and then interface data latch VSTL. The contents of: · VSTH are used for coarse adjustment · VSTL are used for fine adjustment. At the beginning of the first tsub period following the loading of VSTL, both data latches are loaded into data latch VSTREG. After the contents of VSTH and VSTL are latched into VSTREG, one tsub period is needed to generate the appropriate pulse pattern. To ensure correct DAC conversion, two (2) tsub periods should be allowed before beginning the next sequence.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, full pagewidth
"MOV instruction" "MOV instruction"
DATA LATCH VSTH
DATA LATCH VSTL
7
7
DATA LOAD TIMING PULSE
LOAD
DAC DATA LATCH VSTREG
7
7
COARSE PWM OUT1 OUT2
FINE
polarity control bit
ADD Q Q
TDAC output P14LVL Q14 - 8 14-BIT COUNTER
MCD177
Q7 - 1 f0
Fig.10 Block diagram of the 14-bit PWM DAC.
tr
handbook, full pagewidth
t sub0
t sub1
t subn
t sub127
OUT 1
MCD313
t 0 x (VSTH+1)
Fig.11 Coarse adjustment output (OUT1).
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
tr
handbook, full pagewidth
t sub0
t sub16
t sub32
t sub48
t sub64
t sub80
t sub96
t sub112
t sub127
111 1110
111 1101
111 1011
111 1010
MCD314
VSTL
Fig.12 Fine adjustment output (OUT2).
tr
handbook, full pagewidth
t sub0
t sub16
t sub32
t sub48
t sub64
t sub80
t sub96
t sub112
t sub127
OUT 1
OUT 2
TDAC
MCD315
Fig.13 TDAC output.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
10 AFC INPUT The AFC input is used to measure the level of the Automatic Frequency Control signal. This is achieved by comparing the AFC input signal with the output of a 3-bit DAC as shown in Fig.14. DAC analog switches select one of 8 resistor taps connected between VDD and VSS. Consequently, eight different voltages may be selected (see Table 4). The compare signal AFCC, can be tested to determine whether the AFC input is higher or lower than the DAC level. The AFC input shares the same pin as the Derivative Port line DP1.7. Setting the enable bit AFCE to: · Logic 1, selects the AFC function · Logic 0, selects the Derivative Port DP1.7 function. Table 4
84C44X; 84C64X; 84C84X
Selection of Vref Vref VDD × 0.125 VDD × 0.250 VDD × 0.375 VDD × 0.500 VDD × 0.625 VDD × 0.750 VDD × 0.875 VDD Vref (for VDD = 5.0 V) 0.625 V 1.250 V 1.875 V 2.500 V 3.125 V 3.750 V 4.375 V 5.000 V
AFC2 AFC1 AFC0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
handbook, full pagewidth
DP1.7
internal bus
COMPARATOR DP1.7 / AFC EN
AFCC
3-BIT DAC
EN
AFC2
AFC1
AFC0
AFCE
MCD178
inner latches
Fig.14 AFC circuit.
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
11 INPUT/OUTPUT (I/O) Each parallel I/O port line may be individually configured using one of three possible I/O mask options. The three I/O mask options are specified below: Option 1 Standard port with switched pull-up current source, Fig.15. Option 2 Open drain, Fig.16. Option 3 Push-pull (output only), Fig.17.
84C44X; 84C64X; 84C84X
Table 5 specifies the possible port option list. When these devices are used for emulation purposes, in order to match the piggy back device provided it is recommended that the port options listed in Table 6 are used.
WRITE PULSE handbook, full pagewidth OUTL / ORL / ANL / MOV TR2 TR3 DATA BUS D MQ D SQ MASTER SLAVE SQ TR1
VDD constant current source 100 µA typ. I/O PORT LINE
VSS
ORL / ANL / MOV
MLA696
IN / MOV
Fig.15 Standard output with switched pull-up current source (Option 1).
WRITE PULSE
handbook, full pagewidth OUTL / ORL / ANL
VDD D MQ D SQ I/O PORT LINE
DATA BUS
MASTER
SLAVE SQ TR1
V SS
ORL / ANL
MLA697
IN
Fig.16 Open drain type I/O (Option 2).
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
WRITE handbook, full pagewidth PULSE OUTL / ORL / ANL TR2 TR3 DATA BUS D MQ D SQ MASTER SLAVE SQ TR1
VDD constant current source 100 µA typ. OUTPUT LINE
VSS
ORL / ANL
MLB998
IN
Fig.17 Push-pull type output (Option 3).
October 1994
17
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
Table 5 User mask programmable port option list PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 DP0.0 DP0.1 DP0.2 DP0.3 DP0.4 DP0.5 DP0.6 DP0.7 DP1.0 DP1.1 DP1.2 DP1.3 DP1.4(2) DP1.5 DP1.6 DP1.7 VOB VOW3 Notes 1. Each pin can be configured to a HIGH (S) or LOW (R) state after power-on-reset. The required state of each pin is therefore specified by R or S. 2. DP1.4 available only with the PCA84C440, PCA84C443, PCA84C640, PCA84C643, PCA84C840 and PCA84C843. PIN 13 14 15 16 17 18 19 20 7 8 10 11 12 1 2 3 4 5 6 40 39 41 38 37 36 34 23 22 9 25 24 3 3 R R OPTION(1) Table 6
84C44X; 84C64X; 84C84X
Port options for the 84C640 in emulation mode PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 DP0.0 DP0.1 DP0.2 DP0.3 DP0.4 DP0.5 DP0.6 DP0.7 DP1.0 DP1.1 DP1.2 DP1.3 DP1.4 DP1.5 DP1.6 DP1.7 VOB VOW3 PIN 13 14 15 16 17 18 19 20 7 8 10 11 12 1 2 3 4 5 6 40 39 41 38 37 36 34 23 22 9 25 24 3 3 R R 2 2 S S 1 1 1 1 1 1 1 1 1 1 1 1 1 OPTION S S S S S S S S S S S S S
October 1994
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Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12 ON SCREEN DISPLAY 12.1 Features 12.4
84C44X; 84C64X; 84C84X
Clock generator
· Display format: 2 rows × 16 characters · Software controlled vertical and horizontal display position · 64 different (mask programmable) characters in ROM · Black box background · Four programmable display character sizes · Four programmable character dot matrix sizes: 6 × 9 and 6 × 13 8 × 9 and 8 × 13 · Half-dot rounding for the whole screen · 4 from 7 colours possible on screen · Clock generator for on screen display function with: RC oscillator LC oscillator, for the various types of PCA84C44X; 84C64X; 84C84X. 12.2 Horizontal display position control
There are two types of oscillators available for the various types. The oscillator is triggered on the trailing edge of HSYNCN when the OSD logic is enabled and stops on the following leading edge of HSYNCN. The OSD oscillator must be externally adjusted to the desired frequency (decreasing the OSD frequency gives broader characters). Before the oscillation frequency can be adjusted HSYNCN must be HIGH (if HLVL = 1). Oscillation stops by setting the HSYNCN pin LOW when HLVL = 1. 12.4.1 RC OSCILLATOR
The RC oscillator is available in the types: PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843. The external RC network is connected between pin 28 and VSS (see Fig.19). 12.4.2 LC OSCILLATOR
The horizontal position counter is incremented every OSD cycle after the programmed level of HSYNCN occurs at the HSYNCN pin. The counter is reset when the opposite polarity of the HSYNCN pulse is reached. 12.3 Vertical display position control
The LC oscillator is available in the types: PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844. The external LC network is connected between pins 28 and 29 (see Fig.20).
The vertical position counter is incremented every HSYNCN cycle and is reset by the VSYNCN signal.
October 1994
19
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, full pagewidth
VSYNCN
VERTICAL DISPLAY POSITION CONTROL
DISPLAY CONTROL MEMORY
DISPLAY CHARACTER DATA MEMORY
HSYNCN HORIZONTAL DISPLAY POSITION CONTROL CHARACTER ROM
CLOCK GENERATOR (1)
CONTROL TIMING GENERATOR
DISPLAY CONTROL
VOB VOW1 VOW2 VOW3 (1) See Figs 19 and 20 for connection of external components.
MCD179
Fig.18 OSD block diagram.
handbook, halfpage
VDD R
handbook, halfpage
C1 DOSC1
DOSC1 C2 C
L1 DOSC2
MCD247 MCD173
VSS
Fig.19 RC oscillator.
Fig.20 LC oscillator.
October 1994
20
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.5 Display data registers
84C44X; 84C64X; 84C84X
The display data registers consists of a group of 32 derivative registers located at addresses 20H to 3FH inclusive (see Table 7). At power-up the contents of the display data registers are undefined. The format of each display data register is shown in Table 8, and their functions described in Table 9. Table 7 Display data registers addresses DISPLAY DATA FOR Row 0 = the first display row Row 1 = the second display row BIT 7 CC1 BIT 6 CC0 BIT 5 MD5 BIT 4 MD4 BIT 3 MD3 BIT 2 MD2 BIT 1 MD1 BIT 0 MD0
ADDRESS 20H to 2FH 30H to 3FH Table 8 7 CC1 Table 9
Display data register (address 20H to 3FH) 6 CC0 5 MD5 4 MD4 3 MD3 2 MD2 1 MD1 0 MD0
Description of display data register bits SYMBOL CC1 CC0 MD5 MD4 MD3 MD2 MD1 MD0 FUNCTION Colour code. The state of these two bits enable individual characters to be displayed in one of four colours. See Tables 24, 25 and 26. Character code. The character set is stored in ROM and consists of 64 different characters. The selection of each character is dependent on the state of the 6 bits, MD0 to MD5.
BIT 7 6 5 4 3 2 1 0 12.6
Display control registers
The display control registers consists of a group of 6 derivative registers located at addresses 40H to 45H inclusive (see Table 10). Each register may be read from or written to. After a reset operation the contents of the display control registers are zero. Table 10 Display control registers addresses ADDRESS 40H 41H 42H 43H 44H 45H REGISTER OSDCA LINE 0A LINE 0B OSDCB LINE 1A LINE 1B BIT 7 CC34 SZ01 BLK0 CDTW SZ11 BLK1 BIT 6 CC24 SZ00 VB0 CDTH SZ10 VB1 BIT 5 CC14 VP05 HP05 CC33 VP15 HP15 BIT 4 RBLK VP04 HP04 CC23 VP14 HP14 BIT 3 ROUND VP03 HP03 CC32 VP13 HP13 BIT 2 STBY VP02 HP02 CC12 VP12 HP12 BIT 1 VLVL VP01 HP01 CC21 VP11 HP11 BIT 0 HLVL VP00 HP00 CC11 VP10 HP10
October 1994
21
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.6.1 DERIVATIVE REGISTER OSDCA
84C44X; 84C64X; 84C84X
Table 11 Derivative register OSDCA (address 40H) 7 CC34 6 CC24 5 CC14 4 RBLK 3 ROUND 2 STBY 1 VLVL 0 HLVL
Table 12 Description of OSCDA bits BIT SYMBOL 7 6 5 4 CC34 CC24 CC14 RBLK Raster blanking control (see Fig.24). When the RBLK bit is: Logic 1, the VOB output is driven HIGH to display the OSD characters on a blank screen. Logic 0, the VOB output returns to its normal output state on the trailing edge of VSYNCN. 3 ROUND Character rounding control (see Figs 22 and 23). The rounding function generates half dots where the corners of two dots meet. The rounding function also works with multiple cell characters. When the ROUND bit is: Logic 1, the rounding function is enabled. Logic 0, the rounding function is disabled. 2 STBY Stand-by. This bit is used to enable or disable the OSD facility. When the STBY bit is: Logic 1, the OSD oscillator is disabled. Logic 0, the OSD oscillator is enabled and the OSD facility is available. 1 VLVL Vertical synchronous signal level (see Fig.21). This bit selects the active level of the VSYNCN input signal. When the VLVL bit is: Logic 1, VSYNCN is active HIGH. Logic 0, VSYNCN is active LOW. 0 HLVL Horizontal synchronous signal level (see Fig.21). This bit selects the active level of the HSYNCN input signal. When the HLVL bit is: Logic 1, HSYNCN is active HIGH. Logic 0, HSYNCN is active LOW. FUNCTION Character colour code bits. These bits are used for colour selection purposes. See Table 24.
handbook, full pagewidth
HSYNCN (VSYNCN)
(HLVL = VLVL = 1)
HSYNCN (VSYNCN) characters can be displayed
(HLVL = VLVL = 0)
MCD180
Fig.21 VSYNCN and HSYNCN active level.
October 1994
22
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
ook, full pagewidth
ROUND = 0 H H
ROUND = 1
handbook, halfpage
H
H
H T T T
H
MCD181
T
T
T
MCD246
Fig.22 Rounding function.
Fig.23 Rounding effect.
handbook, full pagewidth
RBLK
VSYNCN
VOB
VOW1, 2, 3
MCD316
= normal output
Fig.24 Raster blanking timing RLBK.
October 1994
23
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.6.2 DERIVATIVE REGISTERS LINE 0A AND LINE 0B FUNCTION
84C44X; 84C64X; 84C84X
REGISTER LINE 0A LINE 0B
Determine the character size and vertical position of Row 0 (the first display row). Determine the horizontal position of Row 0 and the selection of background and blanking functions.
Table 13 Derivative register LINE 0A (address 41H) 7 SZ01 6 SZ00 5 VP05 4 VP04 3 VP03 2 VP02 1 VP01 0 VP00
Table 14 Description of LINE 0A bits BIT SYMBOL 7 6 5 4 3 2 1 0 SZ01 SZ00 VP05 VP04 VP03 VP02 VP01 VP00 FUNCTION Character size. The state of these two bits enable one of four possible character sizes to be selected for Row 0. Character sizes include background. See Table 23. Vertical position control. The vertical position of Row 0 is selected by the state of the 6 bits, VP00 to VP05. For details see Section 12.7.1 "Vertical position".
Table 15 Derivative register LINE 0B (address 42H) 7 BLK0 6 VB0 5 HP05 4 HP04 3 HP03 2 HP02 1 HP01 0 HP00
Table 16 Description of LINE 0B bits BIT SYMBOL 7 BLK0 FUNCTION Blanking. This bit enables or disables the character display. When BLK0 is set to: Logic 1, the outputs VOW1, VOW2, VOW3 and VOB are enabled; characters are displayed. Logic 0, the outputs VOW1, VOW2, VOW3 and VOB are disabled; no characters are displayed. 6 VB0 Background. This bit determines whether the background display is selected or not. The visual effect of background versus no background is shown in Fig.26. When VB0 is set to: Logic 1, the characters in this row are displayed with background. Logic 0, the background is disabled and only the characters are displayed. 5 4 3 2 1 0 HP05 HP04 HP03 HP02 HP01 HP00 Horizontal position control. These 6 bits determine the start position of Row 0. The horizontal position control is only active during OSDC clock cycles. For details Section 12.7.2 "Horizontal position" and Fig.25.
October 1994
24
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.6.3 DERIVATIVE REGISTERS LINE 1A AND LINE 1B FUNCTION
84C44X; 84C64X; 84C84X
REGISTER LINE 1A LINE 1B
Determine the character size and vertical position of Row 1 (the second display row). Determine the horizontal position of Row 1 and the selection of background and blanking functions.
Table 17 Derivative register LINE 1A (address 44H) 7 SZ11 6 SZ10 5 VP15 4 VP14 3 VP13 2 VP12 1 VP11 0 VP10
Table 18 Description of LINE 1A bits BIT SYMBOL 7 6 5 4 3 2 1 0 SZ11 SZ10 VP15 VP14 VP13 VP12 VP11 VP10 FUNCTION Character size. The state of these two bits enable one of four possible character sizes to be selected for Row 1. Character sizes include background. See Table 23. Vertical position control. The vertical position of Row 1 is selected by the state of the 6 bits, VP10 to VP15. For details see Section 12.7.1 "Vertical position".
Table 19 Derivative register LINE 1B (address 45H) 7 BLK1 6 VB1 5 HP15 4 HP14 3 HP13 2 HP12 1 HP11 0 HP10
Table 20 Description of LINE 1B bits BIT SYMBOL 7 BLK1 FUNCTION Blanking. This bit enables or disables the character display. When BLK1 is: Logic 0, the outputs VOW1, VOW2, VOW3 and VOB are disabled; no characters are displayed. Logic 1, the outputs VOW1, VOW2, VOW3 and VOB are enabled; characters are displayed. 6 VB1 Background. This bit determines whether the background display is selected or not. The visual effect of background versus no background is shown in Fig.26. When VB1 is set to: Logic 1, the characters in this line are displayed with background. Logic 0, the background is disabled and only the character is displayed. 5 4 3 2 1 0 HP15 HP14 HP13 HP12 HP11 HP10 Horizontal position control. These 6 bits determine the start position of Row 1. The horizontal position control is only active during OSDC clock cycles. For details Section 12.7.2 "Horizontal position" and Fig.25.
October 1994
25
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.6.4 DERIVATIVE REGISTER OSDCB FUNCTION Determine the selection of: · The size of the dot matrix grid · Four colours from a possible seven for the display. Table 21 Derivative register OSDCB (address 43H) 7 CDTW 6 CDTH 5 CC33 4 CC23 3 CC32
84C44X; 84C64X; 84C84X
REGISTER OSDCB
2 CC12
1 CC21
0 CC11
Table 22 Description of OSDCB bits BIT SYMBOL 7 CDTW FUNCTION Character dot width control.The state of this bit determines the dot width of the character. When the CDTW bit is set to: Logic 1, the character width is 6 dots. Logic 0, the character width is 8 dots. 6 CDTH Character dot height control. The state of this bit determines the dot height of the character. When the CDTH bit is set to: Logic 1, the character height is 13 dots. Logic 0, the character height is 9 dots. 5 4 3 2 1 0 CC33 CC23 CC32 CC12 CC21 CC11 Colour control bits. In every VSYNCN cycle one screen can select any 4 colours from 7 and in addition a blank or black screen. Combinations of CC1X, CC2X and CC3X control the character outputs VOW1, VOW2 and VOW3 as shown in Table 24.
October 1994
26
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.7 12.7.1 OSD display position VERTICAL POSITION 12.7.2
84C44X; 84C64X; 84C84X
HORIZONTAL POSITION
The horizontal start position (HP) of, · Row 0: HP0 = 4 × ( HP00 HP05 ) + 5 × t OSCD · Row 1: HP1 = 4 × ( HP10 HP15 ) + 5 × t OSCD Where: · (HP00 HP05) = the decimal value of HP00 HP05 and (HP00 HP05) > 10 · (HP10 HP15) = the decimal value of HP10 HP15 and (HP10 HP15) > 10 · tOSCD = one OSCD clock period. Therefore for both Row 0 and Row 1, HP0, HP1 45 × tOSCD.
The line number of the vertical start position for: · Row 0 is 4 × (VP00 VP05) · Row 1 is 4 × (VP10 VP15). Where: · (VP00 VP05) = the decimal value of VP00 VP05 · (VP10 VP15) = the decimal value of VP10 VP15. The character height in: · Row 0 is H0 and is a function of the number of dots per character and the state of the size control bits SZ00 and SZ01 · Row 1 is H1 and is a function of the number of dots per character and the state of the size control bits SZ10 and SZ11. Row 0 and Row 1 must not overlap each other and therefore: VP1 (VP0 + H0); see Fig.25. The four possible character heights are shown in Table 23.
ok, full pagewidth
VP0 HP0 ROW 0 CHARACTERS H0 VP1
handbook, halfpage
HP1 ROW 1 CHARACTERS with background
MCD182
without background
MCD183
Fig.25 Display position.
Fig.26 Background versus no background.
October 1994
27
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.8 12.8.1 OSD character size and colour selection CHARACTER SIZE
84C44X; 84C64X; 84C84X
The character sizes are selected by bits SZn1 and SZn0, which denotes: · SZ01 and SZ00 for Row 0 · SZ11 and SZ10 for Row 1.
The character sizes are determined by the bits: · CDTW, for the width · CDTH, for the height.
Table 23 Character sizes selection H denotes one horizontal line, T denotes one OSDC clock period and D denotes dots per character width/height. SIZE BITS SZn1 0 0 1 1 12.8.2 SZn0 9D 0 1 0 1 COLOUR SELECTION 18H 36H 54H 72H 13D 26H 52H 78H 104H 6D 12T 24T 36T 48T 8D 16T 32T 48T 64T 2H 4H 6H 8H 2T 4T 6T 8T CHARACTER SIZE VERTICAL HORIZONTAL VERTICAL HORIZONTAL DOT MATRIX POINT
Colour selection is achieved using bits in the, · OSDCA register: CC34, CC24 and CC14 · OSDCB register: CC33, CC23, CC32, CC12, CC21, and CC11 · Display data registers: CC1 and CC0.
In this way every combination of four colours can be made (black and white can not be displayed at the same time). The user may choose one colour out of each block. Table 24 shows the selection of the output combinations. Tables 25 and 26 show the possible colour combinations.
handbook, full pagewidth
CHARACTER ROM
dot
VOW1
CC1 DISPLAY DATA MEMORY CC0
OUTPUT CONTROL LOGIC
VOW2
DISPLAY CIRCUIT CONTROL REGISTERS
CCxx
VOW3
background control
MCD184
OR
VOB
Fig.27 Colour control.
October 1994
28
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
Table 24 Character colour control COLOUR CODE CC1 0 0 1 1 CC0 0 1 0 1 VOW1 (Red) CC11 CC12 CC23 + CC33 CC14
84C44X; 84C64X; 84C84X
CHARACTER OUTPUT PINS1 VOW2 (Green) CC21 CC12 + CC32 CC23 CC24 VOW3 (Blue) CC11 + CC21 CC32 CC33 CC34
Table 25 Possible colour combinations (CC1, CC0) = (0, 0) COLOUR VOW1 VOW2 CC11 Blue Green Red Yellow Magenta Cyan 0 0 1 1 - - CC21 0 1 0 1 - - VOW3 CC11+CC21 1 0 0 0 - - (CC1, CC0) = (0, 1) VOW1 CC12 0 0 1 - 1 - VOW2 CC12+CC32 0 1 0 - 0 - (CC1, CC0) = (1, 0) VOW2 CC12+CC32 0 1 0 - - 1 VOW3 CC32 1 0 0 - - 1
VOW3 VOW1 CC32 1 0 0 - 1 - CC12 0 0 1 - - 0
Table 26 Possible colour combinations (continued) (CC1, CC0) = (1, 1) COLOUR VOW1 CC14 Blue Green Red Yellow Magenta Cyan White Black 0 0 1 1 1 0 1 0 VOW2 CC24 0 1 0 1 0 1 1 0 VOW3 CC34 1 0 0 0 1 1 1 0
October 1994
29
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
12.9 Character ROM 13
84C44X; 84C64X; 84C84X
EMULATION MODE
Character ROM contains the dot character fonts. 13 x 8 dots are reserved for each character, regardless of the dot matrix size actually selected. The dot matrix grid is shown in Fig.28. Philips provides a software under MS DOS environment (IBM/PC or compatible) to help customer to design the character font on the screen and to generate the bit pattern HEX decimal file automatically. Contact your local Philips Sales Organization for details.
The emulation mode configuration is shown in Fig.29. In the emulation mode configuration the PCA84C640's CPU is disabled and only its derivative logic is active. The device is controlled by the PCF84C00 bond-out chip. The PCA84C640's two derivative ports act as additional ports for the PCF84C00. The interaction between the two devices is as follows: 1. During the first machine cycle the PCF84C00 fetches an instruction from EPROM and then decodes that instruction. 2. During the second machine cycle the PCF84C00 executes the decoded instruction. If the instruction is related to the derivative ports then DXALE, DXRDN and/or DXWRN become active and the PCA84C640 operates as a peripheral of the PCF84C00. 3. Depending on the type of instruction executed during the second machine cycle the following data transfer happens: a) During TS1 data from the EPROM is available on P0.0 to P0.7 which is then available on IB0.0 of the PCF84C00. b) During TS4 data from the PCA84C640 can be transferred to the PCF84C00. c) During TS6 data from the PCF84C00 can be transferred to the PCA84C640.
1
handbook, halfpage
2
3
4
5
6
7
8
1 2 3 4 5 6 7 8 9 10 11 12 13
MCD185
Fig.28 Character ROM.
October 1994
30
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, full pagewidth
P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7
PSEN address bus A0 - A12 data bus D0 - D7
CE A0 - A12 D0 - D7
PCF84C00
STFF XTAL1 RESET XTAL2 DXALE DXRD DXWR
EPROM
MCD317
XTAL1 RESET
P1.0 P1.1 P1.2 P1.3
PCA84C640
DP0.0 - DP0.7 P0.0 - P0.7 DP1.0 - DP1.7 TEST/EMU + 5V
Fig.29 Emulation mode configuration.
October 1994
31
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
14 REGISTER MAP The number within parentheses denotes the initial state; `X' denotes don't care. R = Read, W = Write, R/W =Read/Write. ADDR 00H 01H 02H 03H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 20H to 3FH REG DP0 (pin) DP1 (pin) DP0R (latch) DP1R (latch) PWM1 PWM2 PWM3 PWM4 PWM5 VSTL VSTH AFCO AFCC DP0E/ PWME DP1E/ PWMLVL BIT 7 DP0.7 (X) DP1.7 (X) DP0.7 (1) DP1.7 (1) - - - - - - - - - SCLE (0) - BIT 6 DP0.6 (X) DP1.6 (X) DP0.6 (1) DP1.6 (1) - - - - - VST06 (0) VST13 (0) - - SDAE (0) - CC0 (X) BIT 5 DP0.5 (X) DP1.5 (X) DP0.5 (1) DP1.5 (1) PWM15 (0) PWM25 (0) PWM35 (0) PWM45 (0) PWM55 (0) VST05 (0) VST12 (0) - - PWM5E (0) - MD5 (X) BIT 4 DP0.4 (X) DP1.4(1) (X) DP0.4 (1) DP1.4(1) (1) PWM14 (0) PWM24 (0) PWM34 (0) PWM44 (0) PWM54 (0) VST04 (0) VST11 (0) - - PWM4E (0) AFCE (0) MD4 (X) BIT 3 DP0.3 (X) DP1.3 (X) DP0.3 (1) DP1.3 (1) PWM13 (0) PWM23 (0) PWM33 (0) PWM43 (0) PWM53 (0) VST03 (0) VST10 (0) - - PWM3E (0) P14LVL (0) MD3 (X) BIT 2 DP0.2 (X) DP1.2 (X) DP0.2 (1) DP1.2 (1) PWM12 (0) PWM22 (0) PWM32 (0) PWM42 (0) PWM52 (0) VST02 (0) VST09 (0) AFC2 (0) - PWM2E (0) P6LVL (0) MD2 (X) BIT 1 DP0.1 (X) DP1.1 (X) DP0.1 (1) DP1.1 (1) PWM11 (0) PWM21 (0) PWM31 (0) PWM41 (0) PWM51 (0) VST01 (0) VST08 (0) AFC1 (0) - PWM1E (0) VOW2E (0) MD1 (X) BIT 0 DP0.0 (X) DP1.0 (X) DP0.0 (1) DP1.0 (1) PWM10 (0) PWM20 (0) PWM30 (0) PWM40 (0) PWM50 (0) VST00 (0) VST07 (0) AFC0 (0) AFCC (X) TDACE (0) VOW1E (0) MD0 (X) R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W
DATA CC1 DISPLAY (X) MEMORY
October 1994
32
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
ADDR 40H 41H 42H 43H 44H 45H Note
REG OSDCA LINE0A LINE0B OSDCB LINE1A LINE1B
BIT 7 CC34 (0) SZ01 (0) BLK0 (0) CDTV (0) SZ11 (0) BLK1 (0)
BIT 6 CC24 (0) SZ00 (0) VB0 (0) CDTH (0) SZ10 (0) VB1 (0)
BIT 5 CC14 (0) VP05 (0) HP05 (0) CC33 (0) VP15 (0) HP15 (0)
BIT 4 RBLK (0) VP04 (0) HP04 (0) CC23 (0) VP14 (0) HP14 (0)
BIT 3 ROUND (0) VP03 (0) HP03 (0) CC32 (0) VP13 (0) HP13 (0)
BIT 2 STBY (1) VP02 (0) HP02 (1) CC12 (1) VP12 (1) HP12 (1)
BIT 1 VLVL (0) VP01 (0) HP01 (0) CC21 (0) VP11 (0) HP11 (0)
BIT 0 HLVL (0) VP00 (0) HP00 (0) CCV11 (0) VP10 (0) HP10 (0)
R/W R/W R/W R/W R/W R/W R/W
1. These bits are not available in the PCA84C441, PCA84C444, PCA84C641, PCA84C644, PCA84C841 and PCA84C844. 15 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI IOH IOL Ptot Tstg Tamb supply voltage input voltage (all inputs) maximum source current for all port lines maximum sink current for all port lines total power dissipation storage temperature operating ambient temperature (for all devices) PARAMETER MIN. -0.3 -0.3 - - - -55 -20 MAX. +7.0 -10 -30 900 +125 +70 V mA mA mW °C °C VDD + 0.3 V UNIT
October 1994
33
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
16 DC CHARACTERISTICS VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = -20 to +70 °C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD operating supply voltage operating supply current fOSDCRC = fOSDCLC = fXTA L; VDD = 5 V; see note 1; fXTAL = 10 MHz fXTAL = 6 MHz fOSDCRC = fOSDCLC = ST OP; VDD = 5 V; see note 1; fXTAL = 10 MHz fXTAL = 6 MHz IDD(ID) supply current Idle mode VDD = 5 V; fXTAL = 10 MHz fXTAL = 6 MHz; see note 1 IDD(ST) Inputs IIH VIL VIH ILl HIGH level input current (pin RESET) Vin = 0.5 V 20 - - - µA supply current Stop mode VDD = 5.5 V; see notes 1 and 2 - - - 1.3 0.8 5 3 1.5 10 mA mA µA - - - 5 3.5 10 8 mA mA 4.5 5.0 5.5 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
- -
3 1.5
7 3.5
mA mA
PORTS P0, P1, DP0, DP1, HSYNCN AND VSYNCN LOW level input voltage HIGH level input voltage VSS < VI < VDD - ±0.01 - ±0.2 ±10 ±10 µA µA 0 0.3VDD V VDD V 0.7VDD -
PORTS P0, P1, DP0, DP1, INTN/T0 AND T1 input leakage current Ports P0, P1, DP0 and DP1 Ports INTN/T0 and T1 Outputs: Ports P0, P1, DP0, DP1; VOB and VOW3 (see Figs 30, 31 and 31) IOL LOW level output sink current Port P0 Ports P1, DP0 and DP1 Ports VOB and VOW3 PORTS P0, P1, DP0 AND DP1 (see Figs 33 and 33) IOH HIGH level pull-up output source current VO = VSS VO = 0.7VDD HIGH level push-pull output source current VO = VDD - 0.4 V OUTPUTS VOB AND VOW3 (see Fig.33) IOH HIGH level push-pull output source current VO = VDD - 0.4 V 1.2 3 - mA - 40 3 140 100 7 400 - - µA µA mA VO = 1.2 V VO = 0.4 V VO = 0.4 V 10 5 1.2 - 10 3 - - - mA mA mA
October 1994
34
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - -
MAX.
UNIT
AFC characteristics; Port DP1.7/AFC VAI VAE Notes 1. VIL = VSS; VIH = VDD; all outputs and sense input lines unloaded. All open drain ports connected to VSS. 2. Crystal is connected between XTAL1 and XTAL2; T1 = VSS; INT/T0 = VDD. 17 AC CHARACTERISTICS VDD = 5 V; Tamb = -20 to +70 °C; all voltages with respect to VSS; unless otherwise specified. SYMBOL Oscillator fXTAL fOSC-XTAL fOSC-PXE fOSC-XTAL fOSC-PXE fOSC-XTAL fOSC-PXE CXTAL1 crystal frequency; note 1 oscillator frequency; option 1 oscillator frequency; option 2 oscillator frequency; option 3 external capacitance at XTAL1 with XTAL resonator with PXE resonator CXTAL2 external capacitance at XTAL2 with XTAL resonator with PXE resonator fDOSC Note 1. Oscillator with three (3) options for optimum use. on-screen-display clock frequency - 4.0 not required 30 8.0 100 10.0 pF pF MHz - not required 30 100 pF pF gm = 0.4 mS (typ.) gm = 1.6 mS (typ.) gm = 4.5 mS (typ.) 1 1 4.0 1.0 3.0 - - - - - 10.0 6.0 10.0 6.0 10.0 MHz MHz MHz MHz MHz MHz MHz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT comparator analog input voltage conversion error range VSS - VDD ± 0.5 V LSB
not allowed
not allowed
October 1994
35
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
17.1 Characteristic curves
MLC004
84C44X; 84C64X; 84C84X
handbook, halfpage
40 I OL (mA) 34
handbook, halfpage
10 I OL (mA) 8
MLB999
(1) (2)
28
(1) 6 (2) (3) 4
22
(3)
16 2
10
4 0 Port P0; VO = 1.2 V. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C. 2 4 V DD (V) 6
0 0 2 4 V DD (V) 6
Ports P1, DP0 and DP1; VO = 0.4 V. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C.
Fig.30 Typical LOW level output sink current as a function of the supply voltage.
Fig.31 Typical LOW level output sink current as a function of the supply voltage.
handbook, halfpage
10
MLC002
I OL (mA)
handbook, halfpage
200
MLC001
I OH (mA)
8 (1) 6 (2) (3) 4
160 (1) (2) 120 (3)
80
2
40
0 0 2 4 V DD (V) 6
0 0 2 4 V DD (V) 6
Outputs VOW1, VOW2, VOW3 and VOB; VO = 0.4 V. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C.
Ports P0, P1, DP0 and DP1; VO = VSS. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C.
Fig.32 Typical LOW level output sink current as a function of the supply voltage.
Fig.33 Typical HIGH level pull-up output source current as a function of the supply voltage.
October 1994
36
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
84C44X; 84C64X; 84C84X
handbook, halfpage
200 I OH (mA) 160
MLC005
MLC003
handbook, halfpage
5
I OH (mA)
4 (1)
(1) (2)
120
(2) (3)
3
(3)
80
2
40
1
0 0 2 4 V DD (V) 6
0
0
2
4
V DD (V)
6
Ports P0, P1, DP0 and DP1; VO = 0.7VDD. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C.
Outputs VOW1, VOW2, VOW3 and VOB; VO = VDD - 0.4 V. (1) Tamb = -20°C. (2) Tamb = 25°C. (3) Tamb = 80°C.
Fig.34 Typical HIGH level pull-up output source current as a function of the supply voltage.
Fig.35 Typical HIGH level pull-up output source current as a function of the supply voltage.
October 1994
37
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
18 PACKAGE OUTLINE
84C44X; 84C64X; 84C84X
handbook, full pagewidth
seating plane
39.0 38.4 4.57 5.08 max max
15.80 15.24
3.2 2.9
0.51 min 1.73 max 1.778 (40x) 1.3 max 0.53 max 0.18 M 0.32 max 15.24 17.15 15.90
42
22
MSA268 - 1
14.1 13.7
1
21
Dimensions in mm.
Fig.36 Plastic shrink dual in-line package; 42 leads (600 mil); SDIP42 (SOT270-1).
October 1994
38
Philips Semiconductors
Product specification
8-bit microcontrollers with OSD and VST
19 SOLDERING 19.1 19.1.1 Plastic dual in-line packages BY DIP OR WAVE 19.1.2
84C44X; 84C64X; 84C84X
REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 20 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
October 1994
39