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5 4 3 2 1
M ode l ZP1 M/B BOARD
MODEL REV CHANGE LIST
Page FM TO
1 1A
ZP1 M/B BOARD First Release
1A 2 1A
3 2A
Reference ECN E200305-1522 4 3A
D
2A D
5 3C
6 3I 3J
Reference ECN E200306-0644
2B 7 2A
8 2B
Reference ECN E200306-1596 9 3A
2C
10 1A
11 3A
Reference ECN E200307-0524
3A 12 2A
13 2A
Reference ECN E200307-3020 14 2A
3B
15 2A
16 3I 3J
Reference ECN E200308-0364
3C 17 3A
18 1A
C Reference ECN E200308-0959 19 3G C
3D
20 3C
21 2A
Reference ECN E200308-2158
3E 22 3D
23 3A
Reference ECN E200309-0195 24 3F 3J
3F
25 2A
26 2A
Reference ECN E200309-1215
3G 27 2A
28 3I
Reference ECN E200309-1599 29 3I
3H
30 3B
31 3E
Reference ECN E200309-2620
3I 32 3C
B B
Reference ECN E200310-1092
3J
A A
PROJECT : ZP1 PCBA NO.31ZP1MB0002 REV:3J DOC. NO: 204
Quanta Computer Inc.
APPROVED BY : Jason Liu CHECK BY: Jason Liu DRAWING BY: Roger Lee DATE : 10/13/2003 SHEET 1
5 4 3 2 1
5 4 3 2 1
X 'TA L
1 4 .318M
ZP1 M/B SYSTEM BLOCK CPUCLK PCI ..CLOCK
DIAGRAM G CLK CK-GEN
AMD Processor ( Socket A ) VCC_CORE V CLK IC S 950902 3V
P3 2.5V DC/DC 19V IN
P4,5 14.318M
D
D DRCLK D
P30,P31
ADDR
CTRL
DATA
5V,3V,CPUCORE VCC etc.
USB48M
X 'TA L
27M POWER IN Battery
ADDR
CTRL
DATA
CRT
5V
Charger P29
P15
EXT. VGA AGP BUS PCICLK
S-VIDEO ATI M9+X 200/266/333/400MHZ
DDR
P15 ( Option ) DIMM H/W
North Bridge MONITOR
V IN
2.5V
INTA VIA KN400 GCLK
2.5VSUS
SMDDR_VTERM
THERMAL DIODE IN
P22
LCD/INV 3.3V P14 VCC_CORE
1.5V
DDR
CONN P14 2.5V
2.5VSUS
USB48M DIMM
3.3V P6,7,8 P10 2'nd FAN
C P22 C
CH7019
TV ENCODER V-LINK
& LVDS P14 266/533MB/s
5V
HDD UltraDMA 100/133 PCI BUS
P21
Super South
5V VCLK
CD-ROM VIA
P21
MII
3V VT8235
3VSUS LAN PHY PCMCIA 1394
5V
USB 2.0
2.5V MINI-PCI
USB RVCC P11,12,13 14.318M
VT6103 3V
TI1410 TSB43AB21 3V
CONN P22
LPC
X 'TA L RVCC P25 3VSUS
5VSUS
12V P18 3V P23 3VSUS
5VSUS
P24
25M
PCICLK I NTB I NTB I NT C/D
B
R EQ0 R EQ1 R EQ2 B
G NT0 G NT1 G NT2
A D18 A D19 A D20
AC97 X 'TA L
14.318M
Audio 32.768K SIO
Realtek AC'97 Link RJ45
Amplifier PC87393
ALC202 Primary
3V
P16 P25 PCICLK
G1421 3V P19
5V P20 5V Slot0
14.318M P18 X 'TA L
PCICLK PCICLK 2 4 .576M
5V 5V 3V
EC/KBC LPT FDD IR
RJ11 MDC PC87570 Port P17 P16 P16
1394
AC'97 Link 5VPCU P26
P25
3V
5V Secondary
X 'TA L CONN
P23
3VSUS 32.768K
P19
A A
Touch
Keyboard FAN PROJECT : ZP1
Pad P14 BIOS P14 5V P22
5V 5VPCU P26 Quanta Computer Inc.
Size D o cument Number Rev
C us tom 1A
Block Diagram
Date: Wednesday, October 22, 2003 Sheet 1 of 32
5 4 3 2 1
1 2 3 4 5 6 7 8
Voltage Rails Core voltage for Processor ON S0~S1 ON S3 ON S4 ON S5 Control signal
A A
VCC_CORE Core voltage for Processor X VR_ON
SMDDR_VTERM 1.25V for DDR Termination voltage X MAINON
SMDDR_VREF 1.25V for DDR Reference Voltage X MAINON
1.5V X MAINON
PCI DEVICE IDSEL# REQ/GNT# Interrupts
2.5VSUS X X SUSON
2.5V X MAINON
CB1410 AD18 -REQ0/-GNT0 INTB
3VPCU X X X X VL
3VSUS X X SUSON TSB43AB21 AD19 -REQ1/-GNT1 INTB
3V X MAINON
B 5VPCU X X X X VL MINI-PCI AD20 -REQ2/-GNT2 INT C/D B
5VSUS X X SUSON
5V X MAINON
AGP INTA
12V X MAINON
12VOUT X X X X VL
RVCC X X X RVCC_ON
V IN P O W E R SOURCE X X X X
C C
D D
PROJECT : ZP1
Quanta Computer Inc.
Size Document Number R ev
A4 INFORMATION 1A
Date: W ednesday, October 22, 2003 Sheet 2 of 32
1 2 3 4 5 6 7 8
A B C D E
C 694 1 2 1 0 U/1 0 V
+
C 754 2 1 . 1U
C 717 2 1 . 1U
C 740 2 1 1 0 0 0P
C 707 2 1 .0 1 U
C 711 2 1 .0 1 U
L41
3V
D V C C LK R 356 1 2 22 A C9 7 _ 1 4M (19)
1
T I2 0 1 2 0 9 G121 C 705
4 4
1 0 0 0P R 357 1 2 22 A P ICCL K S B (1 3 )
R 361 1 2 22 G CL K 1 4 (8)
2
U33
5 1 F S0 R 360 1 2 22
VDDAGP FS0/REF0 R E F CK 1 1 4 M _ S IO (1 6 )
16 56 R 359 1 2 22 O S CS B (1 3 )
L43 VDDPCI VTT_PG#/REF1
22
AVDD48 F S3 U S B CL K
3V
D V D D C LK 23 20 R 1 41 1 2 33 U S B CL K (1 1 )
VDD FS3/48MHZ F S2
55 21
VDDREF FS2/24_48MHZ
1
1
T I2 0 1 2 0 9 G121 C 761 C 760 51
VDDCPU3 V L CL K S B
+ C 763 MODE/AGPCK0
6 V CL K 0 R 1 16 1 2 33 V L CL K S B (1 3 )
.1 U .0 1U L42 1 2 0 V C C L K 2 D5 50 7 G C LK0 R 3 66 1 2 33 G C L K NB
2 .5 V G C L K NB (8)
2
1 0 U/1 0 V VDDCPU2P5 SEL408/AGPCK1
ITEM 93, Rev.B SBPCLK change
2
1
9 10 F S1 R 1 22 1 2 33 S B P CL K to connect PCI_F
GNDAGP FS1/PCI_F S B P CL K (1 1 )
1
+ C 7 42 13 11 P C I1
GNDPCI SEL_SD_DDR/PCI1
2
2
C 762 24 12 P CMP CL K 0 R 3 82 1 2 33 P CMP CL K
GND MULTSEL/PCI2 L P CP CL K 0 L P CP CL K P CMP CL K (1 8 )
ITEM 41, Rev.B C 714 C 715 1 0 U/1 0 V . 1U 19 14 R 1 30 1 2 33
L P CP CL K (1 6 )
2
2
1 5 P _ NC 1 5 P _ NC GND48 PCI3 R P CL K _ 1 3 9 4 33 P CL K _ 1 3 94
change from 15P to 1 2 15 R 3 86 1 2 P CL K _ 1 3 94 (2 3 )
1
GND PCI4 R M I N I P CL K 33 M I N IP CL K
NC 54 17 R 1 33 1 2 M I N IP CL K (2 4 )
Y 2 1 4 .3 1 8 M HZ GND PCI5
47
GND RCP U C LK- R 120 10
52 1 2 C P U C LK- (4)
CPUCLKC RCP U C LK+ R 123 10
CPUCLKT
53 1 2 C P U CL K + (4) ITEM 23, Rev.B
48 R H C L K NB + R 114 1 2 10 H C L K NB + modify
C K GE N1 4 M _ I CPUT_CS R H C L K NB - H C L K NB - H C L K NB + (6)
3 49 R 118 1 2 10
C K GE N1 4 M _ O X1 CPUC_CS H C L K NB - (6)
R 354 1 M _ NC 4
X2
45 D C L K O (7)
S MDA T BUF_IN DCL K_I R 384 22
(1 0 ,1 2 ) S MDA T 28 46 1 2 D C L K I (7)
S MCL K SDATA FBOUT R _ M CL K 0 + R 125 10 M CL K 0 +
(1 0 ,1 2 ) S MCL K 27 44 1 2 M CL K 0 + (10)
SCLK DDRCKT0 R _ M CL K 0 - R 131 10 M CL K 0 -
43 1 2 MCL K 0 - (10)
3V R 402 10K -IC SPD DDRCKC0 R _ M CL K 1 + R 134 10 M CL K 1 +
3 26 42 1 2 MCL K 1 + (10) 3
A GP CL K R A GP CL K RST/PD# DDRCKT1 R _ M CL K 1 - R 140 10 M CL K 1 - V L CL K S B C 302
(14) A GP CL K 8 41 1 2 MCL K 1 - (10) 1 2 1 0 P _ NC
R 368 33 PCI_STP/AGPCK2 DDRCKC1 R _ M CL K 2 + R 146 10 M CL K 2 +
T30 18 38 1 2 MCL K 2 + (10)
CLK_STP/PCI6 DDRCKT2 R _ M CL K 2 - R 149 10 M CL K 2 - G C L K NB C 713
37 1 2 MCL K 2 - (10) 1 2 1 0 P _ NC
V C C L K 2 D5 DDRCKC2 R _ M CL K 3 + R 150 10 M CL K 3 +
40 36 1 2 MCL K 3 + (10)
VDD3/2P5 DDRCKT3 R _ M CL K 3 - R 151 10 M CL K 3 - A GP CL K C 718
34 35 1 2 M CL K 3 - (10) 1 2 1 0 P _ NC
VDD3/2P5 DDRCKC3
1
1
1
1
1
32
C 7 37 C 743 C 722 C 758 C 721 DDRCKT4
39 31
1 0 0 0P .0 1 U .0 1U . 1U . 1U GND DDRCKC4 U S B CL K C 319
33 30 1 2 1 0 P _ NC
2
2
2
2
2
GND DDRCKT5
29
DDRCKC5
25
IREF S B P CL K C 307
MODE,PIN6 1 2 1 0 P _ NC
(Latched Input) PIN26 PIN18 PIN8
I C S 9 5 0 9 0 2 DG P CMP CL K C 731 1 2 1 0 P _ NC
0 PD# R 403 L P CP CL K C 312 2 1 0 P _ NC
CPU_STOP# PCI_STOP# 1
C L K _ IRE F
P CL K _ 1 3 94 C 735 1 2 1 0 P _ NC
1 RESET# PCICLK6 AGP2 4 7 5 /F
M I N IP CL K C 313 1 2 1 0 P _ NC