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1 11
2 12
L3327
3.3VCONFIG J0JHC0000075
IC3314
TVRP843 ! HDE-BOARD TXNHDE1VZTE (2/3)
C3419 C3422 C3425
CONFIG ROM 6.3V 6.3V 16V
10u 10u 0.1u
R3489 R3490
10k 10k
1 nCS 8
VCC
C3413
FOR
IC3342
3
16V (FIN)
0.1u
2 DATA 7 FACTORY
GND(FIN)
VCC
H2 USE C0DBEHG00006
R3649
PLL 1.2V
OUT
ADJ
CTL
47
Vcc
3 VCC 6 EPCS_DCLK 1
DCLK DCLK
GND
5
4
2
1
2 R3439
C3398 R3473
16V 4 5 EPCS_ASD R3517 47 33k
470 GND
0.1u ASDI 3 R3433
CONF_DONE
open collector 10k
4 TP3360
R3438
VCC(TRGT) FREQ1
RESET 2.8V
TVRP843 1 XIN
FREQ1
8 L3329 20k L3326
J0JHC0000075 J0JHC0000075
5
4
5 XIN
IC3312
nCONFIG R3488
Vcc Vout
+
nCE 10k XOUT FREQ0
6 2 XOUT 7
C0EBE0000066 SUB
R3650 FREQ0
47 EPCS_DATA
NC GND 7 L3322
RESET DATAOUT
VSS VDD
3.3VAnalog J0JHC0000075
1
2
3
3 VSS 6 C3408 C3407 C3406 C3403 C3405 C3415 C3424 C3404 C3418
EPCS_NCS 8 16V 16V
nCS VDD 4V 6.3V 10V 16V 16V 10V 6.3V
0.1u 0.01u 100u 10u 1u 0.1u 0.1u 1u 10u
R3651 C3400 C3399 C3455 C3460
9 ASDI SEL 4 5 CKOUT 10 50V 16V 6.3V 16V
R3478 SEL 1000p 0.1u 10u 0.1u
47 CKOUT
10 GND
3
C3402
10V
1u IC3343
C0ZBZ0001561
CPG
R3400
R3641
R3644
10k
10k
10k
POWER BLOCK(1.2V/3.3V/GND) LVDS_OUT
SEL
IC3341 K15 IO S0
4 L3370
1.2V
IC3341 K16 IO O_CLK 13
IC3341
J0JHC0000075
IC3341 K8 VCCINT
IC3341 L15 IO S2 R3427 82 LVDS_BE3
3.3VFPGA IC3341 J10 VCCINT IO E2 IC3341
C1ZBZ0003575 IC3341 L16 IO S1 C3480
6.3V
C3527
50V
C3526
50V
C3523
50V
C3522
50V
C3448
50V
C3447
50V
C3446
50V
C3432
50V IC3341 J7 VCCINT IO E1 IC3341
R3428 82 LVDS_GO2
R3475 10u 1000p 1000p 1000p 1000p 1000p 1000p 1000p 1000p R3429 56 LVDS_CLKIN1
10k
INIT_DONE IO N13 IC3341 ALTERA CYCLONE2 (BGA) IC3341 H10 VCCINT IO D2 IC3341
IC3341 H7 VCCINT
DEV_CLR IO B3 IC3341
R3487 CLK Pin IC3341 G9 VCCINT
R3423
10k IC3341 F11 VCCD_PLL2 EXB2HV820JV
nSTATUS M13 IC3341 LVDS_DE1
NCONFIG IC3341 H2 CLK0 IC3341 L6 VCCD_PLL1 IO D1 IC3341
nCONFIG J5 IC3341 LVDS_VSYNC1
IC3341 H1 CLK1 IO C2 IC3341
nCSO IO F4 IC3341 C3521 C3520 C3450 C3449 C3445 C3444 C3443 C3427 LVDS_HSYNC1
EPCS_DCLK IC3341 J2 CLK2 16V 16V 16V 16V 16V 16V 16V 16V IO C1 IC3341
DCLK H4 IC3341 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u LVDS_BE7
EPCS_DATA IC3341 J1 CLK3 IO C4 IC3341
DATA0 F1 IC3341 LVDS_BE6
EPCS_ASD IC3341 H16 CLK4 IC3341 N5 GND_PLL1 IO D4 IC3341
ASDO IO C3 IC3341 LVDS_BE5
IC3341 H15 CLK5 IC3341 L5 GND_PLL1 IO C5 IC3341
nCE G5 IC3341 LVDS_BE4
IC3341 J15 CLK6 IC3341 F12 GND_PLL2 IO D5 IC3341
CONF_DONE L13 IC3341 FPGA_CLK LVDS_BO1
R3521 1k IC3341 J16 CLK7 IC3341 D12 GND_PLL2 IO C6 IC3341
TDI H5 IC3341
R3647 1k
TCK F2 IC3341
R3646 1k
TMS G1 IC3341 R3424
EXB2HV820JV
TDO G2 IC3341 L3343 1.2V(PLL) LVDS_BE1
IO D6 IC3341
J0JHC0000075 LVDS_BE0
MSEL1 K12 IC3341
R3471 1k TEST_Pin IC3341 M5 VCCA_PLL1 IO A3 IC3341
LVDS_BO0
R3472 1k C3442 C3441 C3434 IO A4 IC3341
MSEL0 J13 IC3341 R3482 10k 6.3V 16V 50V LVDS_GO1
IC3341 F3 IO 10u 0.1u 1000p IO B4 IC3341
R3484 10k LVDS_GO0
IC3341 F13 IO IO A5 IC3341
R3485 10k LVDS_RO1
IC3341 E14 IO IC3341 M6 GNDA_PLL1 IO B5 IC3341
R3486 10k LVDS_RO0
IC3341 M1 IO IO A6 IC3341
R3515 10k LVDS_BO3
TMDS_RX => FPGA IC3341 M15 IO 1.2V(PLL) IO B6 IC3341
VSYNC R3519 10k L3344
IC3341 M2 IO IC3341 M16 IO J0JHC0000075
HSYNC IC3341 E12 VCCA_PLL2
IC3341 N1 IO
DE R3425