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PAMS Technical Documentation NSE­8/9 Series Transceivers

Chapter 2 System Module

Issue 1 07/99

NSE­8/9 System Module

PAMS Technical Documentation

Contents Page No
Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charger Initiated Power Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . Power Button Initiated Power Up Procedure . . . . . . . . . . . . . . . . . . . Real Time Clock Initiated Power Up Procedure . . . . . . . . . . . . . . . . . Power Down Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets and Watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband supplies, CCONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband ADC's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAD2PR1 system ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buzzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vibra, NSE­9 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­ 5 2­ 6 2­ 7 2­ 7 2­ 10 2­ 21 2­ 31 2­ 34 2­ 34 2­ 34 2­ 35 2­ 36 2­ 37 2­ 40 2­ 41 2­ 42 2­ 45 2­ 47 2­ 50 2­ 53 2­ 53 2­ 58 2­ 59 2­ 59 2­ 62 2­ 68 2­ 69 2­ 69 2­ 70 2­ 70 2­ 71

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RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSM900 Front­End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSM1800 Front­End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Receiver parts for GSM900 and GSM1800 . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Transmitter Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSM900 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSM1800 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Power Control for GSM900 and GSM1800 . . . . . . . . . . AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFC function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Module GF7_17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2­ 72 2­ 74 2­ 75 2­ 76 2­ 77 2­ 78 2­ 78 2­ 80 2­ 81 2­ 81 2­ 82 2­ 83 2­ 84 2­ 84 2­ 85 2­ 85 2­ 86 2­ 88 2­ 88

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Table of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. SIM connector, X100 and Battery terminals, . . . . . . . . . . . . . . Display Connector pin location . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Connector, X503, pin locations (top View) . . . . . . . . . . Bottom Connector, X503, pin locations (BottomView) . . . . . . . Internal Speaker Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vibra Motor­connetion pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . DC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Principle of SMR power Functions . . . . . . . . . . . . . . . . . . . . . . Charging Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . Sim Card DetX detection levels . . . . . . . . . . . . . . . . . . . . . . . . . Memory Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interface ­ CCONT and MAD2PR1 . . . . . . . . . . . . . . . Digital Interface ­ COBBA_GJP and MAD2PR1 . . . . . . . . . . UI Switch & Transducers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Frequency Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synthesiser­ Block Diagram . . . . . . . . . . . . . . . . . Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­ 10 2­ 12 2­ 15 2­ 15 2­ 19 2­ 20 2­ 31 2­ 40 2­ 41 2­ 43 2­ 44 2­ 46 2­ 47 2­ 56 2­ 57 2­ 58 2­ 60 2­ 61 2­ 68 2­ 73 2­ 74 2­ 75 2­ 77 2­ 80 2­ 85 2­ 86

Schematics/Layouts (GF7_17) Connections between RF and Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRFU3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Layout ­ Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Layout ­ Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A ­1 A ­2 A ­3 A ­4 A ­5 A ­6 A ­7 A ­8 A ­9 A ­10 A ­11

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Technical Information
HD947 is a DCT3.5 based product, i.e. a dual band GSM 900 & DCS1800, single board concept using the serial version of the MAD2PR1­ and COBBA_GJP chip set. HD947 is based on HD945 (PICA) HW with significant modifications in the Baseband as listed below:
­ HD947 uses a two cell semi fixed NiMH battery­pack only, giving 2.4V nominal supply voltage. Thus the usual NMP battery interface is modified. ­ A special charge control ASIC, PSCC, is used for two cell NiMH charging instead of CHAPS (basically a Chaps modified for 2cells with reduced features). ­ The supply voltage inside the phone is delivered by a DC/DC converter, which step up the battery voltage to 3.1 ­ 4.2 V supplying the regulators and PA's of the phone. ­ The DC/DC converter is supplying 4 different voltages ref. depending upon the required power level and phone state. ­ HD947 has a special non DCT3 compatible Bottom connector, which supports no DATA, only chargers and external audio. ­ Headset HDC­5 and Handsfree unit PPH­1 are supported. ­ The external Audio is dual ended uplink and downlink. ­ HD947 supports only internal vibra, and in NSE­9 only. ­ No support of FLASH ROM writing outside production or aftersales environment. ­ HD947 has a separate serial EEPROM. ­ Battery removal detection is changed compared to previous NMP standard. ­ An integrated switch IC, UISwitch, is used for buzzer, vibra and backlight driving. ­ There are no backup supply for the RTC. The watch may have to be reset after battery removal.

The only difference in the Baseband between GF7 and GD7 is that "Col 4" pin on the MAD2PR1 is logically HIGH in GF7 and logically LOW in GD7, to indicate to the SW which kind of PCB is in use. The two different versions are made to accommodate the use of two different sets of PA's. The only Baseband difference between NSE­8 and ­9 is that the vibra is mounted in the mechanical assembly in NSE­9.

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Operating Modes
1.

Acting Dead: If the phone is off and the switcher is operating with the lowest output voltage and a charger is connected, the Baseband is powered on but enters a state called "acting dead". To the user the phone acts as if it was switched off. A battery charging alert is given and/or a battery charging indication on the display is shown to acknowledge the user that the battery is being charged. Active Mode: In the active mode the phone is in normal operation, scanning for channels, listening to a base station, transmitting and processing information. The switcher delivers output voltage level depending upon whether the TX is active and on what power level or if the TX is not active. All the CCONT regulators are operating. There are several sub­states in the active mode depending on if the phone is in burst reception, burst transmission, if DSP is working etc.. Deep Sleep Mode: In the sleep mode all the regulators except, Vcobba, Vref, VBB, (Vcore when MAD2PR1 in C07 is used) and the SIM card VSIM regulators are off. Sleep mode is activated by the MAD2PR1 after MCU and DSP clocks have been switched off. The voltage regulators for the RF section are switched off and the VCXO power control, VCXOPwr is set low. In this state only the 32 kHz sleep clock oscillator in CCONT is running. The flash memory power down input is connected to the VCXO power control, so that the flash is deep powered down during sleep mode. In sleep mode the switcher supplies minimum output voltage. The sleep mode is exited either by the expiration of a sleep clock counter in the MAD2PR1 or by some external interrupt, generated by a charger connection, key press, headset connection etc. The MAD2PR1 starts the wake up sequence and sets the VCXOPwr control high. After VCXO settling time other regulators and clocks are enabled for active mode. If the battery pack is disconnect during the sleep mode, the CCONT shall power down the SIM in the sleep mode as there is no time to wake up the MCU.

2.

3.

4.

Power Off mode: In this mode all Baseband circuits are powered off. The DC/DC converter is still running supplying the lowest output voltage. Thus the CCONT is powered in the same way as in usual DCT3 products when the phone is powered off and battery remains connected.

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Maximum ratings
Table 1. Maximum ratings Parameter Battery voltage, idle mode Charger input voltage Temperature range Rating ­0.3 ... 3.6 V ­5.0 ... 18V Condition Max voltage at which the battery can be charged by the phone Max voltage which activates the PSCC input over­voltage protection

DC Characteristics
Table 2. Battery & DC/DC converter Voltages Line Symbol Battery Supply voltage Converter startup voltage Signal Name Vb Vb Min 1.9 1.2 1.4 Converter shutdown voltage Output over voltage protection Power on SW limit, normal mode Power on SW limit, acting dead mode Battery cut off voltage (SW) Vb Vdc_out Vb Vb Vb 1.2 4.8 2.15 2.15 1.9 Typ 2.4 1.4 1.6 1.4 Max 3.6 1.6 1.85 1.6 6.5 Unit V V V V V V V V V109a release level V105 start up level V109a activation level V109b activation level Comments

Table 3. DC/DC converter output voltages when in TX­mode Line Symbol Vdc_out current in TX burst @Vdc_out min * Current between burst @3.3V Condition ** Vcon1 Vcon2 "L" "L" 3.1 n/a *) 3.3 n/a *) 3.5 1120 V *** mArms Min Typ Max Unit @ Power level in 900MHz 11 ­19 1800MHz 5 ­ 15

n/a *)

n/a *)

150

mArms

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Table 3. DC/DC converter output voltages when in TX­mode Line Symbol Vdc_out current in TX burst @Vdc_out min * Current between TX burst Vdc_out current in TX burst @Vdc_out min * Current between TX burst Vdc_out current in TX burst @Vdc_out min * Current between TX burst Vdc_out "H" "H" "H" "H" "L" "H" Condition ** Vcon1 Vcon2 "H" "L" 3.2 n/a *) 3.4 n/a *) 3.6 1360 V *** Min Typ Max Unit

(continued) @ Power level in 900MHz 9 ­10 1800MHz 3­4

mArms

n/a *)

n/a *)

150

mArms

3.7 n/a *)

3.9 n/a *)

4.1 2650

V *** mArms

7­8

0­2

n/a *)

n/a *)

150

mArms

3.8 n/a *)

4.0 n/a *)

4.2 2900

V *** mArms

5­6

N/A

n/a *)

n/a *)

150

mArms

3.8

4.0

4.2

V

for buzzer & vibra alerting

*) Note: Maximum load of Vdc_out during TX burst, when Vdc_out is not allowed to drop below 3.05V, Cout is 20% below nominal and remaining load besides PA is max. 150mA. **) Note: The SW control makes converter voltage step up before PA power consumption level is increased, and makes converter voltage stay up until PA power consumption is lowered. ***) Note: Voltage with no load, voltage will drop during burst, but with the stated current voltage will not drop below 3.05V.

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Table 4. DC/DC converter output voltages when non Tx­mode Line Symbol Vdc_out Vdc_out Vdc_out Vdc_out Vdc_out Condition Vcon1 Vcon2 Low Low Low Low high Low Low Low Low high 3.1 3.1 3.1 3.1 3.8 3.3 3.3 3.3 3.3 4.0 3.5 3.5 3.5 3.5 4.2 V V V V V Off mode Sleep mode Active mode non TX Acting dead mode for buzzer & vibra operation Minimum Nominal Maximum Unit Comment

Table 5. Actual Regulated Baseband supply Voltages * Line Symbol Vbb Baseband supply voltage Signal Name Vbb Min. 2.7 Typ 2.8 15 25 COBBA analog supply voltage Vcobba 2.67 2.8 10 7 MAD2PR1 core voltage * Vcore ­5 % 1.98 Max. 2.87 25 125 2.85 20 80 +5 % TBD TBD MAD2PR1 core voltage * Vcore ­5 % 1.5 +5 % TBD TBD 5V SIM supply voltage Vsim 4.8 5.0 10 3V SIM supply voltage Vsim 2.8 3.0 10 Reference Voltage Vref 1.4775 1.5 5 5.2 20 3.2 20 V mVac_pp mArms V mVac_pp mArms V Vac_pp mArms V Vac_pp mArms V mVac_pp V mVac_pp V ripple V ripple V ripple for MAD2PR1 in C07 ripple ripple no audio input output @ start up with MAD2PR1 C07 ripple ripple Unit Notes

1.5225 V 15 mVac_pp

*) Note: The values will be updated when C07 devices are available. With MAD2PR1 Vcore is not used.

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External Signals and Connections
This section lists and specifies all the electrical connections from the Baseband part of the transceiver, i.e. either to the outside world (Bottom­ , SIM card­ and battery connector) , or to items in the mechanical assembly that has electrical interface (LCD, Vibra, speaker and microphone).

Table 6. external connectors Parameter SIM Connector Battery connectors Display Connector Bottom connector Speaker Connector Vibra motor connector X100 X101 & X102 X400 X503 B201 E103 & E104 connector

4 X102 Vb 5 X101 GND 1 X100 6

3 4 3 5 2 6 1 2

Figure 1.

SIM connector, X100 and Battery terminals, X101 & X102, pin locations

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Table 7. SIM Connector , X100 Pin 1 2, 6 3 Name GND VSIM DATA Parameter GND 5V SIM Card 3V SIM Card 5V Vin/Vout 3V Vin/Vout 4 SIMRST 5V SIM Card 3V SIM Card 5V SIM Card 3V SIM Card 5 SIMCLK Frequency Trise/Tfall Min 0 4.8 2.8 4.0 0 2.8 0 4.0 2.8 0 0 5.0 3.0 "1" "0" "1" "0" "1" "1" "0" "0" 3.25 25 Typ Max 0 5.2 3.2 VSIM 0.4 VSIM 0.4 VSIM VSIM 0.4 0.4 V V V V MHz ns SIM clock SIM reset not active SIM reset V SIM data Trise/Tfall max 1us Unit V V Notes Reference ground for the SIM interface signals Supply voltage

VSIM supply voltages are specified to meet type approval requirements regardless the tolerances in components.
Battery connectors Table 8. Battery Connectors, X101 & X102 Pin 1, 2 Name PGND X101 VB X102 Parameter Power ground d Battery Voltage Min 0 Typ Max 0 5 1.8 2.4 3.6 5 Unit V mW V mW Total contact resistance Supply to the DC/DC converter Total contact resistance Notes

3, 4

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Display connector

Pad 8

Pad 1

Figure 2.

Display Connector pin location

Table 9. Display connector, X400 P i n Signal Symbol Parameter Min. Typ. Max. Unit Notes

1 VBB

Supply voltage

2.7

2.8

3.3 300

V uA

range that LCD supports +25 °C, VL= 2.8 V, LCDCSX is disabled with Special Test Pattern "12345"

2 GenSIO_0 fEXT tscyc tshw tslw ViH ViL tr / tf 3 GenSIO_1 tsds tsdh ViH

Serial clock input

0 250 100 100 0.7xVbb 0

1.083

4.00

MHz ns ns ns

Vbb 0.3xVbb 10

V V ns ns ns

Logic high Logic low Rise / fall time

Serial data input

100 100 0.7xVbb Vbb

V

Logic high

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Table 9. Display connector, X400 P i n Signal Symbol Parameter Min. Typ.

(continued) Max. Unit Notes

ViL tr / tf 4 LCDCD tsas tsah ViL ViH tr / tf 5 LCDEN tcss tcsh ViH ViL tr / tf 6 GND 7 VOUT GND Ground LCD output voltage Chip select input Control/display data flag input

0

0.3xVbb 10

V ns ns ns

Logic low Rise / fall time Setup time Hold time Logic low, Control data Logic high, Display data Rise / fall time

100 100 0 0.7xVbb 0.3xVbb Vbb 10 60 100 0.7xVbb 0 Vbb 0.3xVbb 10 0 3xVbb 6.82 9 9

V V ns ns ns V V ns V V V

Logic high Logic low, active Rise / fall time In LCD interface from voltage booster inside LCD driver from voltage booster inside LCD driver Philips display from voltage booster inside LCD driver Logic high, not active Logic low, active width for valid reset pulse driver initialization time after reset Rise / fall time

9 8 LCDRSTX ViH ViL trw tinit tr / tf Reset 0.7xVbb 0 100 1000 10 Vbb 0.3xVbb

V V V ns ns ns

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LCDEN

GenSIO_1

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

GenSIO_0

1

2

3

4

5

6

7

8

9

10

LCDCD

Serial interface timing
tcss tcsh

LCDEN
tsas tsah

LCDCD
tscyc tslw

GenSIO_0
tf tsds tr tsdh

tshw

GenSIO_1

Data

Detailed Serial Interface timing

trw

LCDRSTX

tinit

Driver internal state

In reset

Ready

Driver Reset timing

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Bottom Connector

2, IMICP D­cover to PCB gronund

Microphone well 3, IMICN

D­cover to PCB gronund 1 Charge_GND Mic sound port 4,5,6,7,8 Audio Jack

13, V_charge_in Pad 10,11,12 Charger Jack 9, Charge_Ctrl, pad

Figure 3.

Bottom Connector, X503, pin locations (top View)

Charge_GND 1 D­cover to PCB GND

Mic sound port

Audio Jack 4,5,6,7,8

Charge_ctrl 9 Charger Jack 10,11,12

13, V_charge_in Pad D­cover to PCB GND

D­cover to PCB GND

1

2 15

3 15 4

11 5 6 7 8 9 10 12 13

D­cover to PCB GND

Figure 4.

Bottom Connector, X503, pin locations (BottomView)

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Table 10. Signals of the bottom connector X503 Pin 1, 10 2 Name Charge _GND IMICP Parameter Charger return IMICP Min ­0.3 0.55 Typ Max 0 4.1 Unit V mV Notes W.R.T GND Connected to COBBA MIC2P/N input. The maximum value corresponds to1 kHz, kHz 0 dBmO network level with input amplifier gain set to 32 dB. typical value is maximum value ­16 dB. No plug inserted in audio jack Plug inserted in audio Jack Output AC impedance (ref. XEarN) HDC­5 f<3400 Hz Output level (ref. XEarN) HDC­5 f<3400 Hz Output AC impedance (ref. XEarN) PPH­1 300< f<3400 Hz

3

IMICN

IMICN

0.55

4.1

mV

4

INT

Headint low Headint high

0.57 Vbbmin 113

0.65 Vbb 150

0.72 Vbbmax 188

V V

5

XEarP *)

positive line for external audio output HDC­5 mode

0.84

Vpp

PPH­1 mode

4.0

4.2

4.4

K

1.8

Vpp_ac Output level (ref. XEarN) PPH­1 f<3400 Hz

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Table 10. Signals of the bottom connector X503 (continued) Pin 6 Name XMicN *) Parameter Negative line for external audio input to phone HDC­5 mode 775 95 ­100 PPH­1 mode 40 895 995 380 ­400 0.5 Min Typ Max 0.025 Unit Vpp Notes Maximum input signal level (ref. XMicP) with Cobba gain 18dB, 300< f <3400 Hz

dB/dec Input attenuation, f<300 Hz (ref. XMicP) mV mV µA Vpp Hook active DC level ref. gnd Hook in­active DC level ref. gnd Bias current (ref. XMicP) Maximum input signal level (ref. XMicP) with Cobba gain 12dB, 300< f <3400 Hz

20 2500

dB/dec Input attenuation, f<300 Hz (ref. XMicP) mV Mute (output DC level), wrt. Charge_gnd without HFM­8 Mute (output DC level), wrt. Charge_gnd with HFM­8 Unmute (output DC level), wrt. charge_ gnd without HFM­8 Unmute (output DC level), wrt. charge_ gnd with HFM­8 See XEarP pin definitions output is symmetrical

2130 2230

mV mV

1850

mV

7

XEarN *)

Negative line for external audio output HDC­5 mode PPH­1 mode

See XEarP pin definitions output is symmetrical

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Table 10. Signals of the bottom connector X503 (continued) Pin 8 Name XMicP *) Parameter Positive line for external audio input to phone HDC­5 mode 1450 40 Min Typ Max 0.025 Unit Vpp Notes Maximum input signal level (ref. XMicN) with Cobba gain 18dB, 300< f <3400 Hz

dB/dec Attenuation of input inside phone, f<300 Hz (ref. XMicN) 2090 mV Headset identification DC level ref. gnd @ AUXout = 2.1V and PDATA_4 ="L" Bias current (ref. XMicN) Maximum input signal level (ref. XMicN) with Cobba gain 12dB, 300< f <3400 Hz

100 PPH­1

400 0.5

µA Vpp

20 2060 2180 2300

dB/dec Input attenuation, f<300 Hz (ref. XMicN) mV PPH­1 with HFM­8 identification DC level, wrt. Charge_gnd @ AUXout = "Z" and PDATA_4 ="L" PPH­1 with out HFM­8 identification DC level, wrt. Charge_gnd @ AUXout = "Z" and PDATA_4 ="L" Charger control PWM low Charger control PWM high PWM frequency for a 3 wire charger PWM duty cycle

2490

2600

2720

mV

9, 12

Charge _Ctrl Ct l

PWM external charge l h control

0 2.4 32 1 25

0.5

V V Hz

99

%

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Table 10. Signals of the bottom connector X503 (continued) Pin 11. 13 Name V_char ge_IN Parameter Charger voltage input, ACP­7 type ACP­8 type ACP­9 type Min 7.25 320 5.7 500 7.1 6.0 720 Typ 7.6 11.1 370 6.0 620 8.4 7.1 800 Max 7.95 16.9 420 1.1 6.3 750 9.3 8.0 850 Unit Vrms Vp mA Apeak Vrms mA Vrms Vrms mA Notes Unloaded ACP­7 Charger Unloaded Peak voltage Supply current Supply current Unloaded ACP­8 Charger Supply current Unloaded & charg_ctrl PWM= 0% Unloaded & charg_ctrl PWM= 25% Supply current 15a Not 15b used 16, 17 Charge _GND Not used Internal short circuit in bottom connector. Not used in NSE­8/9 ­ 0.3 0 V wrt. Supply ground

Charger return

Speaker connection

Pad 1, EarN

Pad 2, EarP

Figure 5.

Internal Speaker Pads

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Table 11. Internal Earpiece connection, B201 Pad 1 Name EARN Min 0 Typ 14 Max 220 Unit mVac Remark Connected to COBBA_GJP EARN output. Typical level corresponds to ­16 dBmO network level with volume control giving nominal RLR (=+2dB) 8 db below max. Max level is 0dBmO with max volume (codec gain ­11 db) Connected to COBBA_GJP EARP output. Typical level corresponds to ­16 dBmO network level with volume control giving nominal RLR (=+2dB) 8 db below max. Max level is 0dBmO with max volume (codec gain ­11 db)

2

EARP

0

14

220

mVac

Vibra motor connection

E104

E103

Figure 6. Vibra Motor­connetion pads

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Table 12. Vibra motor connection, E103 & E104 Pad E103 to E104 E103 to E104 E103 to E104 E103 to E104 E103 to E104 Name Rated current Operating voltage Start voltage Start current internal resistance 10.7 1.2 1.1 135 Min Typ 1.3 116 1.9 Max Unit V mA rms V rms V rms mA rms ohm Comment

E103 to E104 Rated voltage

Internal Signals and Connections
This section describes all the signal between the Baseband blocks Additionally the signals between the Baseband and the RF section are described.
Table 13. Audio Block connections Name of signal charg_ctrl HOOKDET HEADDET XEARP XEARN XMICP XMICN IMICP IMICN EAD SERRFI(3:0) PCM(3:0) COBBACLK COBBA RESET AFC RXC TXC Type input output output output output input input input input output Bus Bus input input output output output Remark connected for schematic reasons (use of TVS on audio sheet) Logical signal indicating whether hook is active or not in accessory Low g g g y equals button activated. Logical output indicating whether the audio accessory is inserted ( g g y (HIGH) ) or not (LOW). Positive line of the external audio downlink signal. Negative line of the external audio downlink signal. Positive line of the external audio uplink signal Negative line of the external audio uplink signal Positive line of the internal microphone signal Negative line of the internal microphone signal Analog voltage used for accessory identification. Serial control for the COBBA_GJP and serial data for the RF interface. Serial digital data for the COBBA_GJP audio System clock for the COBBA_GJP Reset signal to the COBBA_GJP Analog voltage to RF controlling the system frequency Analog voltage for gain control in the RF­receiver (AGC) Analog voltage for the TX ramping control

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Table 13. Audio Block connections Name of signal TXIN TXIP TXQN TXQP RXINP RXINN KEY_LIGHT LCD_LIGHT Type output output output output input input output output

(continued)

Remark Negative line of the in phase transmit signal Positive line of the in phase transmit signal Negative line of the quadrature phase transmit signal Positive line of the quadrature phase transmit signal Positive line of the in phase receive signal Negative line of the in phase receive signal Logical signal controlling the keyboard backlight driver. Logical signal controlling the LCD backlight driver.

Table 14. CPU connections Name of signal PURX SLEEPCLK CCONTINT HOOKDET HEADDET CCONTCSX MBUS Type input input input Input input output bi directional output output bus bus output output output input bus Power on reset 32KHz sleep clock signal for MAD2PR1 operation in sleep state Interrupt line from CCONT to MAD2PR1, for all events in CCONT Logical signal indicating whether the hook button of the accessory is activated or not Logical signal indicating whether an accessory is inserted or not CCONT Chip select for the serial communication with MAD2PR1 Serial communication line between MAD2PR1 and external service or production equipment. Clock line for F­bus communication during flashing. Logical output from MAD2PR1 to the vibra driver in the UISWITCH Control of power up/down of the 13MHz system clock, sleep mode control to CCONT Communication lines between MAD2PR1 and the SIM driver in CCONT Serial clock and data for the communication between MAD2PR1 and CCONT, and from MAD2PR1 to LCD­driver. Logical signal controlling charging through PSCC, High disables start­ and PWM­charging. Logical signal controlling the charger switch inside PSCC, High switch open, Low switch closed Output for serial communication between MAD2PR1 and external service or production equipment. Input for serial communication between MAD2PR1 and external service or production equipment. communication line between MAD2PR1 and COBBA_GJP for cobba control and receive and transmit data for the RF transmission. Remark

VIBRA VCXOPWR SIMIF(4:0) GENSIO(1:0) CHARG_OFF PSCC_PWM FBUS_TX FBUS_RX SERFI(3:0)

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Table 14. CPU connections Name of signal PCM(3:0) COBBACLK COBBA RESET COL(3:0) ROW(4:0) BUZZER LCDCD LCDEN LCDRSTX VCON_1 VCON_2 LOW_BATT BTEMP SDATA SCLK SENA1 FRACTRL TXP RFC BAND_SEL Type bus output output output input output output output output output output Input Input output Output output output output Input output

(continued) Remark

communication line beteween MAD2PR1 and COBBA_GJP for receive and transmit data for the audio transmission. 13MHz clock for the synchronization COBBA Reset signal from MAD2PR1 to Cobba_GJP Column addresses for the keyboard scan Row addresses from the keyboard scan and power­on key. PWM output from MAD2PR1 to the Buzzer driver in UISWITCH Control line to the LCD driver Chip select to the LCD driver Reset of the LCD driver Least significant bit in the 2­bit DAC control of the DC/DC­converter output voltage. Most significant bit in the 2­bit DAC control of the DC/DC­converter output voltage. Battery removal alert to MAD2PR1 connection to provide access to BTEMP signal in production and service Serial data for the synthesizer inside SUMMA in the RF 13/4 MHz clock for the serial communication with the synthesizer inside SUMMA in RF Chip select for the serial communication with SUMMA in RF Controls signal for the gain in the LNA in the RF Logical control signal to indicate the power on of the TX circuitry 13MHz system clock from the RF Logical control of the band selection in the front end GSM 900 or DCS 1800

Table 15. POWER connections Name of signal V_CHARGE_IN CHARGE_GND CHARG_CTRL PSCC_PWM CHARG_OFF Type input input output input input charger voltage input charger current return Charger voltage control signal Logical signal from MAD controlling the charger switch inside PSCC, High switch open, Low switch closed Logical signal from MAD enabling / disabling charging through PSCC, High disables both start­ and PWM­charging. Remark

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Table 15. POWER connections Name of signal GENSIO(1:0) SIMIF(4:0) VCXOPWR CCONTCSX CCONTINT SLEEPCLK PURX VDC_out_2 VRX_1 VRX_2 VSYN_2 VXO VTX VCP VREF VDC_OUT RF_TEMP TXP LOW_BATT EAD PWRON VCON_1 VCON_2 BTEMP Type bus bus input input output output output output output output output output output output output output input input output input input input input output

(continued) Remark

Serial clock and data for communication between CCONT and MAD2PR1, and from MAD2PR1 to LCD­driver 5 signals for MAD2PR1 communication with SIM through CCONT Control from MAD2PR1 to power on/off the 13 MHz oscillator, sleep mode control Chip select for communication with CCONT Common CCONT event interrupt line to MAD2PR1 32KHz clock for MAD2PR1 sleep mode operation Power up reset signal to MAD2PR1 Filtered DC/DC output supply for Synth supply regulator in RF Regulator output for Rx part of CRFU in RF Regulator output for Rx part of SUMMA in RF Regulator output for VCO's and synthezeiser in SUMMA in RF Regulator output for 13 MHz oscillator in RF Regulator output for TX parts in SUMMA and CRFU in RF 5v supply for SUMMA in RF 1.5v common voltage reference for Baseband and RF DC/DC output supply voltage for PA's, backlight, vibra and buzzer Input from temperature sensor in RF TX burst synchronization Battery removal alert to MAD2PR1 external accessory detection, analog voltage to CCONT EAD ADC Phone power on signal to CCONT, watch dog disable DC/DC converter voltage control, LSB of two bit DAC DC/DC converter voltage control, MSB of two bit DAC to test pad to provide access to BTEMP for production and service

Table 16. UI connections Name of signal WDDIS PWRON COL(3:0) ROW(4:0) BUZZER LCDCD Type input output input output input input Remark Connection to panel connector in production for watch dog disable Phone power on signal to CCONT Column addresses for the keyboard scan Row addresses from the keyboard scan and power­on key. Logical input from MAD2PR1 to the Buzzer driver in UISWITCH Control line to the LCD driver

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Table 16. UI connections Name of signal LCDEN LCDRSTX VIBRA KEY_LIGHT LCD_LIGHT GENSIO(1:0) Type input input input input input bus Chip select to the LCD driver Reset of the LCD driver

(continued) Remark

PWM output from MAD2PR1 to the vibra driver in the UISWITCH Logical signal controlling the keyboard backlight driver in the UISwitch. Logical signal controlling the LCD backlight driver in the UISwitch. Serial clock and data for communication between CCONT and MAD2PR1, and from MAD2PR1 to LCD­driver

RF control and interface

The interface signals between the Baseband and the RF section are shown below.
Table 17. Signals within the Baseband controlling the RF Signal name SERRIF 0 From To MAD2PR1 COBBA bi­ directional MAD2PR1 COBBA bi­ directional MAD2PR1 COBBA MAD2PR1 COBBA MAD2PR1 COBBA Parameter Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" Logic high "1" Logic low "0" COBBA­ CLK TXP MAD2PR1 COBBA MAD2PR1 CCONT Logic high "1" Logic low "0" Logic high "1" Logic low "0" Minimum 2.0 0 2.0 0 2.0 0 2.0 0 2.0 0 2.0 0 2.0 0 Typical Maximum Vbb 0.4 Vbb 0.4 Vbb 0.4 Vbb 0.4 Vbb 0.4 Vbb 0.4 Vbb 0.4 Unit V V V V V V V V V V V V V V CSX, chi chip select for SERRFI BUS SD, control data for cobba bb DSPGENOut5 Qdata for RF Function Idata for RF

SERRIF 1

SERRIF 2

SERRIF 3

COBBARESET

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Table 18. AC and DC Characteristics of signals between Baseband and RF Signal name VRX_1 From To CCONT VR2 CRFU3 Parameter DC­voltage voltage ripple when on DC­voltage voltage ripple when on DC­voltage voltage ripple DC­voltage voltage ripple DC­voltage Current voltage ripple when on VCP CCONT V5V SUMMA DC­voltage Current voltage ripple VREF CCONT SUMMA DC­Voltage Current voltage ripple Vdc_out DC/DC­converter output to RF PA's RF CCONT DC­Voltage 5 1.478 10 1.5 4.8 5 5.0 2.67 2.67 2.67 2.67 Minimum 2.67 Typical 2.8 10 2.8 5 2.8 5 2.8 5 2.8 2.85 15 2.85 150 15 5.2 30 ­ Isim 25 1.523 100 10 mA mVpp V uA mVpp Reference voltage for SUMMA Maximum 2.85 15 2.85 15 2.85 Unit V mVpp V mVpp V mVpp V mVpp V mA mVpp for Summa for Tx in Summa & CRFU for VCO's & Synth. i Summa S for 13 MHz oscillator for Rx part of Summa Function for Rx part of CRFU

VRX_2

CCONT VR5 SUMMA

VSYN_2

CCONT VR4 VCO's VCO' CCONT VR1 VCTCXO CCONT VR7 CRFU3

VXO

VTX

RF_TEM P

voltage BB pull up to Vref RF pull down to gnd ADC resolution

0 ­5% 47 47 10

1.5 +5 %

V Kohm Kohm NTC bits Ro = 47Kohm +/­10% Bo = 4050 +/­3%

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Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name AFC From To COBBA_GJP VCTCXO Parameter Voltage Resolution Load resistance (dynamic) Load resistance (static) Noise voltage Settling time RXC COBBA_GJP SUMMA Voltage Min Voltage Max Vout temperature dependence Source impedance active state Source impedance power down state Input resistance Input capacitance Settling time Noise level Resolution DNL INL 10 +/­0.9 +/­ 4 1 10 10 500 0.12 2.27 10 1 500 0.5 0.18 2.33 10 200 Minimum 0.046 11 Typical Maximum 2.254 Unit V bits kohm Mohm uVrms ms V V LSB ohm Receiver gain control 10...10000Hz Function Automatic frequency control signal f t l i l for VCTCXO

grounded

Mohm pF us uVrms bits LSB LSB 0...200 kHz

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Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name TXC From To COBBA_GJP SUMMA Parameter Voltage Min Voltage Max Vout temperature dependence Source impedance active state Source impedance power down state Input resistance Input capacitance Settling time Noise level Resolution DNL INL Timing inaccuracy TXIN / TXIP COBBA_GJP SUMMA Differential voltage swing DC level Differential offset voltage (corrected) Diff. offset voltage temp. dependence Source impedance Load resistance Load capacitance DNL INL Group delay missmatch 40 10 +/­ 0.9 +/­1 100 1.022 0.784 1.1 0.8 10 +/­0.9 +/­ 4 1 1.18 0.816 +/­ 2.0 +/­ 1.0 200 10 10 10 500 Minimum 0.12 2.27 Typical Maximum 0.18 2.33 10 200 Unit V V LSB ohm Function Transmitter power control t l

high Z

kohm pF us uVrms bits LSB LSB us Vpp V mV Differential in­phase TX Baseband signal for the RF modulator d l t 0...200 kHz

mV

ohm kohm pF LSB LSB ns

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Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name TXQN / TXQP From To COBBA_GJP SUMMA Parameter Differential voltage swing DC level Differential offset voltage (corrected) Diff. offset voltage temp. dependence Source impedance Load resistance Load capacitance Resolution DNL INL Group delay missmatch RXIP/ RXIN SUMMA COBBA_GJP Output level Source impedance Load resistance Load capacitance SDATA MAD2PR1 SUMMA Logic high "1" Logic low "0" Load impedance Load capacitance Data rate frequency 3.25 2.0 0 10 10 1 tbd. Vbb 0.5 50 8 +/­ 0.9 +/­1 100 1344 tbd. 40 10 Minimum 1.022 0.784 Typical 1.1 0.8 Maximum 1.18 0.816 +/­ 2.0 +/­ 1.0 200 Unit Vpp V mV Function Differential quadrature phase TX Baseband i l for the d signal f th RF modulator

mV

ohm kohm pF bits LSB LSB ns mVpp ohm Mohm pF V V kohm pF MHz PLL data Differential RX 13 MHz signal t B i l to Baseband b d

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Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name SCLK From To MAD2PR1 SUMMA Parameter Logic high "1" Logic low "0" Load impedance Load capacitance Data rate frequency SENA1 MAD2PR1 SUMMA Logic high "1" Logic low "0" Current Load capacitance FRACT RL MAD2PR1 CRFU Logic high "1" Logic low "0" Current TXP MAD2PR1 SUMMA Logic high "1" Logic low "0" Load Resistance Load Capacitance Timing inaccuracy RFC VC(TC)XO MAD2PR1 Frequency Signal amplitude Load resistance Load capacitance BAND_ SEL MAD2PR1 CRFU 3 Logic high "1" Logic low "0" Current 2.0 0 0.5 10 10 Vbb 0.4 0.1 13 1.0 2.0 2.0 0 50 10 1 2.0 0 2.0 0 3.25 Vbb 0.5 50 10 Vbb 0.4 0.1 Vbb 0.5 Minimum 2.0 0 10 10 Typical Maximum Vbb 0.5 Unit V V kohm pF MHz V V uA pF V V mA V V kohm pF us MHz Vpp kohm pF V V mA
GSM900 DSPGenOut 4 GSM1800

Function PLL clock

PLL enable

Nominal gain in LNA Reduced gain in LNA

Transmitter power control t l enable bl

High stability clock signal f th l i circuits l for the logic i it

NOTE: Logic controls in low state when RF in power off.

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Table 19. NSE­8/9 Baseband key components Name used in this document Cobba_GJP MAD2PR1 FLASH RAM EEPROM PSCC switcher CCONT UISwitch Schematic Ref. N200 D300 D301 D302 D303 N101 V105 N100 N400 Description

Mixed signal RF­ and audio Codec System ASIC with MCU and DSP FLASH ROM Static RAM EEPROM Charger switch control IC DC/DC converter IC Multi functional power management IC Integrated switch IC for UI transducer driving

TX/RX SIGNALS

RF SUPPLIES

13MHz CLK SYSTEM CLOCK

COBBA SUPPLY COBBA_GJP CCONT

SIM

Buzzer vibra motor Backlight
LCD

BB SUPPLY core voltage

32kHz CLK SLEEP CLOCK PA SUPPLY Vdc_out

UI­ Switch

MAD2PR1 DSP MCU

DC/DC­ converter Eprom RAM Flash PSCC

VB NiMH BATTERY

AUDIOLINES BASEBAND Bottom Con

Figure 7.

Baseband Block Diagram

Technical Summary
The Baseband architecture is basically similar to DCT3 GSM phones. HD947 differs from DCT3 in the single pcb concept and the serial interface between MAD2PR1 and COBBA_GJP and between MAD2PR1 and CCONT. In HD947 the MCU, the system specific ASIC and the DSP are

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integrated into one ASIC, called the MAD2PR1 chip, which takes care of all the signal processing and operation controlling tasks of the phone. The Baseband architecture supports a power saving function called "sleep mode". This sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and Baseband. During the sleep mode the system runs from a 32 kHz crystal. The phone is waken up by a timer running from this 32 kHz clock supply. The sleeping time is determined by some network parameters. When the sleep mode is entered both the MCU and the DSP are in standby mode and the normal VCTCXO clock has been switched off. The battery voltage in HD947,called Vb, is 1.8V to 3.6V depending on the battery charge amount. The battery voltage is up converted to one of 4 voltage levels in the range from 3.1 V to 4.2 V, called Vdc_out, by means of a DC/DC converter. The nominal level of the four Vdc_out voltages, depends upon the required power level of the RF. The DC/DC converter is always operating, provided that the input supply is greater than 1.8V and with sufficient current capability. The main part of the Baseband is running from 2.8V power rails, which is supplied by a power controlling asic, CCONT. The supply, Vcobba, for the analog audio parts, and the supply Vbb for the main digital parts of the Baseband along with Vcore as supply possibility for the core of MAD2PR1. In the CCONT asic there are 7 individually controlled regulator outputs for the RF­section. In addition there is one +5V power supply output (V5V), also supplied to the RF. The CCONT also contains a SIM interface, which supports both 3V and 5V SIM­cards. The SIM is supplied from a separate regulator, VSIM, in CCONT. A real time clock function is integrated into the CCONT, which utilizes the same 32kHz clock supply as the sleep clock. The supply for the RTC is taken directly from Vdc_out. Which means that when the battery is removed the RTC may have to be set again at power up. However the RTC will run for at least 24h after the phone has cut off due to low battery power. Last but not least the CCONT supplies a 1.5V reference voltage, Vref, for AD­converter usage in the Baseband and as reference voltage to the RF. The COBBA_GJP asic provides A/D and D/A conversion of the in­phase and quadrature receive and transmit signal paths to the RF along with AFC frequency control, AGC receiver gain control and TXC transmitter power control. The remaining RF control signals are supplied by the MAD2PR1, i.e. BAND_SEL for selection between 900 or 1800 MHz band, FrACtrl for amplification control in the receiver front end, and tree signals

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for the control of the RF synthesizer. The COBBA_GJP asic also provides A/D and D/A conversions of received and transmitted audio signals to and from the internal and external audio transducers.

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Data transmission between the COBBA_GJP and the MAD2PR1 is implemented using two serial busses, SERRFI for RF digital data and COBBA_GJP control. PCM for digital audio data. Digital speech processing is handled by the MAD2PR1 asic. Last but not least the COBBA_GJP emits the backlight control signals to the UISWITCH IC, which drives the keyboard­ and LCD backlight LEDs. The Baseband supports 3 microphone inputs together with 2 earphone outputs. The mic inputs can be taken from an internal microphone, a headset microphone or from an external active microphone signal source. The microphone signals from different sources are connected to separate inputs at the COBBA_GJP asic. The output for the internal earphone is a dual ended type output capable of driving a dynamic type speaker. Input and output signal source selection and gain control is performed inside the COBBA_GJP asic according to control messages from the MAD2PR1. Keypad tones, DTMF, and other audio tones except ringing alert are generated and encoded by the MAD2PR1 and transmitted to the COBBA_GJP for decoding. MAD2PR1 generates a PWM output for the buzzer and a logical high/low signal for driving the internal vibra motor. These control signals together with light control are fed to the UIswitch which drives the backlight, vibra and buzzer units. The MAD2PR1 communicates via an IIC bus with the EEProm which contains all user changeable data and tuning values. Additionally the memory of HD947 is made up of a FLASH Rom and a SRAM for MCU memory, both sharing a common address­ data bus. The DSP memory is completely integrated into the MAD2PR1 asic. Two wire and three wire chargers can be connected to the phone. Three wire chargers are equipped with a control input, through which the phone gives PWM charging control signal to the charger. The battery charging is controlled by two different PWM signals, one from CCONT to the charger, CHARG_CTRL, and one from MAD2PR1 to PSCC, PSCC_PWM. The CHARG_CTRL, is constant 25%, to make the phone the master in case it's inserted into a DCH­9 deskstand. The PSCC_PWM duty cycle is determined by the charging software. A 84 by 48 dot matrix LCD is connected via a zebra connector. The MAD2PR1 commands the display driver via a serial write only interface.

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Baseband
Functional Description
There are four actions that initiate the power up procedure of the phone; 1. pressing the power on/off button
2. 3. 4. connecting a charger to the phone power up initiated by a pulse on BTEMP (DCT3 IBI pulse) power up initiated by RTC

Because the power up procedure is somewhat different depending on the initializing action they are described below separately. The power up procedures are described up to the point when the system control switches from CCONT to MAD2PR1, i.e. when power up reset (PURX) is released. Charger Initiated Power Up Procedure 0. INITIAL CONDITIONS: ­ all components except DC/DC converter and CCONT RTC powered off ­ all resets active ­ battery connected 1. CHARGER ADDED: 1.1 The PSCC starts charging the battery with initial current. When the battery voltage reaches the switcher startup voltage level, the switcher will start up and supply the CCONT 1, which identifies the charger presence (VCHAR) 1.2 1.3 1.4 CCONT waits until Vdc_out exceeds 3.0 V 2 CCONT powers on its digital logic and sets the PWM output to100% CCONT releases the reset of its digital logic after 50 us setup time

2. CCONT RELEASES BB, VCXO and COBBA­ANALOG 3REGULATORS: 2.1 CCONT releases SLEEPX/VXOEna signal 2.2 CCONT waits 62 ms 4 3. AFTER 62 ms DELAY CCONT RELEASES POWER UP RESET (PURX) AND SETS CCONT_INT SIGNAL ACTIVE:
This may take some seconds depending upon the battery / switcher being able to supply sufficient current, if the battery is almost empty, If charger is connected to empty battery this may take some seconds VCXO regulator is controlled by SLEEPX/VXOEna signal. The regulator for the COBBA analog parts must follow the VCXO regulator to enable the AFC 62 ms setup time is used for VCXO settling

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3.1 3.2 3.3 3.4

MAD takes over the system control the SLEEPX signal control switches to MAD MAD notices the CCONT_INT active MAD reads the CCONT interrupt register, identifies the charger interrupt and starts to control the charging

In the end of the power up procedure initialized by adding the charger the phone goes to "POWER ON ACTING DEAD" state. In this state the only indication to the user are the battery charging alert and the scrolling battery mark in the display. In "POWER ON ACTING DEAD" state no actions against GSM network are done, the phone remains unknown to the network. Power Button Initiated Power Up Procedure 0. INITIAL CONDITIONS: ­ all components except DC/DC converter and CCONT RTC are powered off ­ all resets active ­ battery connected with sufficient energy for power up ­ charger is not connected 5 1. POWER BUTTON PRESSED: 1.1 CCONT identifies the PWRONX signal activation 1.2 CCONT checks that the Vdc_out exceeds 3.0 V 1.3 CCONT powers on its digital logic 1.4 CCONT releases the reset of its digital logic after 50 us setup time 2. CCONT RELEASES VBB, VCXO and Vcobba REGULATORS: 2.1 CCONT releases SLEEPX/VXOEna signal 2.2 CCONT waits 62 ms 6 3.a. IF PWRONX ACTIVE AFTER 62 ms DELAY THEN CCONT RELEASES POWER UP RESET (PURX): 3.1 MAD takes over the system control 3.2 the SLEEPX signal control switches to MAD 3.b. ELSE PWRONX NOT ACTIVE AFTER 62 ms THEN CCONT GOES TO POWER OFF: 4.a IF THE KEYBOARD POWER INTERRUPT IS ACTIVE LONG ENOUGH 7THEN THE PHONE GOES TO POWER ON/POWER BUTTON STATE 4.a.1 MAD system logic releases MCU reset 4.a.2 MCU serves the power button interrupt 4.a.3 MCU turns on the SIM regulator (SIMCardPwr)
If charger is connected the phone is not in power off state but in POWER ON ACTING DEAD state and hence this power up procedure is not applicable The 62 ms setup time is used for VCXO settling The time is checked by MCU SW

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4.a.4 4.a.5

MCU turns on the keyboard and display lights MCU performs PIN enquiry i.e. checks if PIN code needs to be asked and if yes, asks it

4.b ELSE THE KEYBOARD POWER INTERRUPT IS NOT ACTIVE LONG ENOUGH THEN THE PHONE STARTS POWER DOWN PROCEDURE In the end of this power up procedure the phone is in a state where it is ready for network synchronization and communication with the user. Real Time Clock Initiated Power Up Procedure The RTC initiated power up procedure is used when a time alarm set in the RTC is reached. The phone will be powered up to the POWER ON/RTC ALARM state. 0. INITIAL CONDITIONS: ­ all components except DC/DC converter and CCONT RTC powered off ­ all resets active ­ battery connected with sufficient energy for power up ­ ALARM value set 1. REAL TIME MATCHES ALARM VALUE: 1.1 RTC logic sends power on command to CCONT analog part 1.2 CCONT checks that Vdc_out exceeds 3.0 V 1.3 CCONT powers on its digital logic 1.4 CCONT releases the reset of its digital logic after 50 us setup time 2. CCONT RELEASES VBB, VXO and Vcobba REGULATORS: 2.1 CCONT releases SLEEPX/VXOEna signal 2.2 CCONT waits 62 ms 3. AFTER 62 ms DELAY CCONT RELEASES POWER UP RESET (PURX) AND SETS CCONT_INT SIGNAL ACTIVE: 3.1 MAD2PR1 takes over the system control 3.2 the SLEEPX signal control switches to MAD2PR1 3.3 MAD2PR1 notices the CCONT_INT active 3.4 MADPR1 reads the CCONT interrupt register and identifies the alarm interrupt 4. THE PHONE GOES TO POWER ON/RTC 4.1 MCU serves the alarm 4.2 MCU turns on the SIM regulator (SIMCardPwr) 4.3 MCU flashes the keyboard and display lights and sounds the alert 4.4 The SW asks IF the alert should be delayed IF navi­key pressed THEN go to INITIAL CONDITION ELSE the SW asks if the phone should be activated for network connection 4.5 MCU performs PIN enquiry i.e. checks if PIN code needs to be

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4.6

asked and if yes, asks it MCU starts communicating with the world

5. POWER ON/RTC: ­ BB regulator active ­ VCXO regulator active ­ COBBA­analog regulator active ­ SIM regulator active ­ MAD controls the system ­ power on indicated to the user In the end of this power up procedure the phone is in "POWER ON/RTC" state where it will indicate the alarm to the user by beeps and/or display information. It shall be noted that the RF part of the phone is not turned on in this state in order to disable the transmissions not controlled by the user. How the phone changes state from "POWER ON/RTC" state to normal operational mode is a matter of MCU SW and UI SW specifications.

Power Down Schemes
There are four ways to power down the phone: 1. by pressing power on/off button,
2. 3. 4. by letting the CCONT watchdog expire, by letting the battery voltage drop below the operation limit (either by not charging the battery or by removing it) by removing the charger (in "POWER ON/ACTING DEAD" state only).

Power button initiated power down procedure

0. INITIAL CONDITIONS: ANY OPERATIONAL STATE 1. POWER BUTTON PRESSED (FOR POWER OFF): 1.1 MCU SW detects that power button is pressed long enough to start power down procedure 1.2 MAD2PR1 (MCU SW) updates and disconnects SIM, close down network and UI connections 2.a IF CHARGER CONNECTED (CCONT_INT ACTIVE ) THEN GO TO "POWER ON ACTING DEAD" STATE: ­ BB regulator active ­ VCXO regulator active ­ COBBA­analog regulator active ­ MAD controls the system and the charging 2.b ELSE SEND POWER OFF COMMAND TO CCONT: 2.b.1 MAD sends power off command (writes short delay to WDOG) 3. POWER DOWN THE SYSTEM 3.1 CCONT waits until the watchdog expires

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3.2

3.3

CCONT activates power up reset (PURX) signal which disables all regulators (system control switches to CCONT at PURX activation) CCONT powers itself off

4. POWER OFF STATE ­ all components except CCONT RTC and DC/DC converter are powered off ­ all resets active There is a delay of 100 us between the expiring of the watchdog and reaching the power off state. During this time CCONT does not accept charger detection nor power on interrupts, i.e. if user generates these interrupts during the 100 us delay they don't have any effect and the phone stays off.
Watchdog Initiated Power Down Procedure

Watchdog initiated power down is typically a result of a phone malfunction, like SW errors, when the CCONT watchdog is not reset by SW. Because of this the watchdog initiated power down can be entered in any operational state. Watchdog can be disabled by HW means by connecting the CCONT WDDisX pin to ground. 0. INITIAL CONDITIONS: ANY OPERATIONAL STATE ­ watchdog enabled 1. CCONT WATCHDOG EXPIRES 2. POWER DOWN THE SYSTEM 2.1 CCONT activates power up reset (PURX) signal which disables all regulators (system control switches to CCONT at PURX activation) 2.2 CCONT powers itself off 3. POWER OFF STATE ­ all components except CCONT RTC and DC/DC converter are powered off ­ all resets active There is a delay of 100 us between the expiring of the watchdog and reaching the power off state. During this time CCONT does not accept charger detection nor power on interrupts, i.e. if user generates these interrupts during the 100 us delay they don't have any effect and the phone stays off.
Battery Voltage Drop Initiated Power Down Procedure

When battery voltage approaches the cutoff voltage the phone will notify the user of the situation. If the user does not charge the battery the battery voltage will eventually drop below the operation cutoff voltage and the

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phone powers off. The power down procedure can be entered from any operational state. A brutal way for power down is to remove a battery when the phone is powered on. The phone gets warning of this by LOW_BATT detection signal which is connected directly to MAD (CARDDETX) . When MAD realizes that battery is being removed it has 2 ­ 4 ms time to power down the SIM interface in order to protect the SIM card. MAD2PR1 forces down the SIM reset, SIM clock, SIM data and SIM power in this order.
Charger Removal Initiated Power Down Procedure

0. INITIAL CONDITIONS: POWER ON/ACTING DEAD STATE 1. CHARGER REMOVED 1.1 MAD gets CCONT_INT interrupt 1.2 MCU reads the status of the CCONT interrupt register and notifies charger removal 1.3 MAD sends power off command (writes short delay to WDOG) 2. CCONT WATCHDOG EXPIRES 3. POWER DOWN THE SYSTEM 3.1 CCONT activates power up reset (PURX) signal which disables all regulators (system control switches to CCONT at PURX activation) 3.3 CCONT powers itself off 4. POWER OFF STATE ­ all components except CCONT RTC and DC/DC converter powered off ­ all resets active

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Clocking Concept This section describes the main clocks in the system.

SIM
SIM CLK

VCXO
13 MHz SINE WAVE

AFC

COBBA_GJP

32 KHZ XTAL

SIM CLK

MAD2PR1
13 MHz

CCONT
RTC

3.25 MHz 32 kHz SLEEP CLOCK GENSIO_0 1.083MHz

13 MHz 520KHz PCM

PLL
52 MHz

8 kHz PCM SYNC 3.25 MHz SYNTE CLK

Summa

DSP

LCD DRIVER
osc
16.3KHz

Figure 8.

Clocking Scheme

The system clock in the HD947 phone is 13 MHz. It is generated in the RF VCTCXO circuit. The clock frequency is controlled by AFC which is in COBBA_GJP. The 13 MHz sine wave signal goes to MAD2PR1 RFC block which generates a square wave signal from the sine wave signal. MAD2PR1 provides the clocks to its internal system components from the 13 MHz system clock. The MCU receives 13 MHz clock. For the DSP the MAD2PR1 system logic provides an 13 MHz clock which is up converted by the DSP PLL 52 MHz. MAD2PR1 generates also the clocks to its own system logic blocks. The real time clock logic consists of RTC logic in CCONT, and the 32 kHz crystal. In normal situation the real time clock takes the power from the switcher output. When the cutoff voltage is reached the switcher continues to operate at least 24h, providing supply for the RTC. In case the main battery is removed the RTC is powered by the output capacitors on the switcher until they are drained and the RTC loses it's timing. The time must be set again upon power on. CCONT generates a 32 kHz sleep clock signal which is used as a time base during the sleep state. The 32 kHz clock signal goes to MAD2PR1 which has the sleep state counter. Sleep clock output to MAD2PR1 is active always when the phone is powered on.

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Cobba_GJP uses the 13 MHz clock,COBBACLK, coming from MAD2PR1 as a system clock. The 520KHz PCM codec master clock,PCMDClk, and the 8 KHz PCM codec frame synchronization clock,PCMSClk, are the two PCM codec related clocks going from COBBA_GJP to MAD2PR1 . The master clock is used to clock the transfer of the PCM samples between COBBA PCM codec and MAD2PR1 DSP. The frame synchronization clock frequency is used to indicate the sample rate of the PCM samples. A 3.25 MHz synthesizer clock, SynthClk, is used to load the synthesizers. The clock is generated in MAD2PR1 and it goes to SUMMA in RF. MAD2PR1 provides the SIM clock, 3.25 MHz, to the SIM card via CCONT SIM interface. The MAD2PR1 general purpose serial output, GenSIO_0, is a 1.083 MHz clock which is used in the communication between MAD2PR1 ­ CCONT and MAD2PR1 ­ LCD driver. The LCD driver IC is equipped with an internal free running clock oscillator of typically 16.3 KHz used for internal logical operation and divided into the display frame frequency of 80 Hz.

Resets and Watchdogs
This section describes the resets and the watchdogs of the system. They are described together because they are linked together, i.e. expired of a certain watchdog causes a certain reset to happen.

SIM
SIM RESET

COBBA_GJP

SIM RESET

CCONT
CCONT WATCHDOG PURX

COBBA

MAD2PR1
SOFT WATCHDOG

RESET

Flash Rom
SYSTEM RESET

LCD DRIVER RESET LCDRSTX

LCD DRIVER
Figure 9. Reset Scheme

RAM

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Power up reset, PURX, is the main reset of the system. It is controlled by the CCONT digital part and is released in the power up. PURX is related to the CCONT watchdog which in turn is the main watchdog of the system. CCONT watchdog is controlled by the MCU SW which has to update it at regular intervals. If the CCONT watchdog expires then PURX goes activate and the power of the phone is turned off. The watchdog maximum value is 64 s and the default value is 32 s. System reset is a general purpose reset and is used to reset the phone at any time when the phone is operating, i.e. PURX is not active. System reset goes asynchronously active if MCU writes the software reset or if the software watchdog expires. System reset follows also the power up reset, i.e. system reset is active when PURX is active. One of the DSP controlled general purpose output lines, DSPGenOut_5 is used for COBBARESET. The reason for having a separate reset for COBBA is to allow the DSP SW to reset COBBA without resetting other parts of the system. Because COBBA reset is a lower level reset than power up reset, system reset and DSP reset, it is activated also when these resets are activated. COBBA reset is released by DSP software. The MCU controlled general purpose I/O line, MCUGenIO_2, is used as the LCD driver reset. MCU SW can activate and release the reset. LCD driver is not connected to the system reset because having a separate reset for it allows resetting the system without the user knowing it. MAD2PR1 generates reset to SIM card, SIMIF_2. The reset goes to the SIM card via the CCONT SIM interface block.

Power Supply
The DC/DC converter is the only unit which draws current from the 2 cell NiMH battery pack. The battery voltage, Vb, is up converted through the DC/DC converter to an output voltage level, Vdc_out, which is dependent on the phone state (operating mode) and in call mode depending upon which band and on what power level the phone is transmitting at. The DC/DC converter feeds power directly to four parts of the system: the CCONT, the power amplifier, the UI (buzzer, Vibra, display­ and keyboard­ lights) and for a separate regulator in the RF. The Baseband contains components that control power distribution to the whole phone, except for the PA control in RF. The battery consists of two NiMH cells and a polyswitch, all assembled into the battery pack. An external charger can be used for recharging the battery and supplying power to the phone. The charger can be either a two wire type of charger, or a 3­wire charger, so called performance charger. The power management circuit PSCC provides protection against over voltages, charger failures and pirate chargers etc. that would otherwise cause damage to the phone.

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RF SUPPLIES

RF reg. PA SUPPLY VSIM

VCOBBA LCD VBB COBBA VBB CCONT PWRONX PWM VBB

SIM

Vdc_out Buzzer LED's Vibra PURX Ctrl

Vdc_out

VBB

Vcore

VBB UISwitch Ctrl VBB

DC/DC Converter

Vcon_1/2 MAD2PR1 VB PSCC PSCC_pwm Charge_off VIN BOTTOM CONNECTOR BATTERY

Figure 10.

Vpp

DC/DC Converter

The DC/DC­converter principal implementation in NSE­8/9 is shown Figure 11. V105 is the switcher