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SN54/74LS375
4-BIT D LATCH
The SN54 / 74LS375 is a 4-Bit D-Type Latch for use as temporary storage
for binary information between processing limits and input /output or indicator
units. When the Enable (E) is HIGH, information present at the D input will be
transferred to the Q output and, if E is HIGH, the Q output will follow the input.
When E goes LOW, the information present at the D input prior to its setup time 4-BIT D LATCH
will be retained at the Q outputs.
LOW POWER SCHOTTKY

CONNECTION DIAGRAM DIP (TOP VIEW)
VCC D3 Q3 Q3 E2,3 Q2 Q2 D2
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
J SUFFIX
has the same pinouts CERAMIC
(Connection Diagram) as CASE 620-09
the Dual In-Line Package. 16
1

1 2 3 4 5 6 7 8
N SUFFIX
D0 Q0 Q0 E0,1 Q1 Q1 D1 GND
PLASTIC
16 CASE 648-08
1
TRUTH TABLE
(Each latch) NOTES:
tn = bit time before enable
tn tn+1 g g g
negative-going transition. D SUFFIX
tn+1 = bit time after enable SOIC
D Q 16
negative-going transition. CASE 751B-03
H H 1
L L

PIN NAMES LOADING (Note a)
ORDERING INFORMATION
HIGH LOW
SN54LSXXXJ Ceramic
D1