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54174 DM54174 DM74174 54175 DM54175 DM74175 Hex Quad D Flip-Flops with Clear
June 1989
54174 DM54174 DM74174 54175 DM54175 DM74175
Hex Quad D Flip-Flops with Clear
General Description Features
These positive-edge triggered flip-flops utilize TTL circuitry Y 174 contains six flip-flops with single-rail outputs
to implement D-type flip-flop logic All have a direct clear Y 175 contains four flip-flops with double-rail outputs
input and the quad (175) version features complementary Y Buffered clock and direct clear inputs
outputs from each flip-flop Y Individual data input to each flip-flop
Information at the D inputs meeting the setup and hold time Y Applications include
requirements is transferred to the Q outputs on the positive- Buffer storage registers
going edge of the clock pulse Clock triggering occurs at a Shift registers
particular voltage level and is not directly related to the tran- Pattern generators
sition time of the positive-going pulse When the clock input Y Typical clock frequency 40 MHz
is at either the high or low level the D input signal has no Y Typical power dissipation per flip-flop 38 mW
effect at the output Y Alternate Military Aerospace device (54174 54175) is
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Connection Diagrams
Dual-In-Line Package Dual-In-Line Package
TL F 6557