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SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the DUAL JK NEGATIVE
J and K inputs may be allowed to change when the clock pulse is HIGH and EDGE-TRIGGERED FLIP-FLOP
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX
CERAMIC
CASE 620-09
16
1
Q Q
5(9) 6(7)
N SUFFIX
PLASTIC
CLEAR (CD) SET (SD) CASE 648-08
16
15(14) 4(10)
J K 1
3(11) 2(12)
1(13)
CLOCK (CP) D SUFFIX
SOIC
16
1 CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
MODE SELECT -- TRUTH TABLE SN74LSXXXN Plastic
SN74LSXXXD SOIC
INPUTS OUTPUTS
OPERATING MODE
SD CD J K Q Q
Set L H X X H L
LOGIC SYMBOL
Reset (Clear) H L X X L H
*Undetermined L L X X H H 4 10
Toggle H H h h q q
Load "0" (Reset) H H l h L H SD SD
11
Load "1" (Set) H H h l H L 3 J Q 5 J Q 9
Hold H H l l q q
1 CP 13 CP
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously. 2 K CD Q 6 12 K C Q 7
D
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
15 14
X = Don't Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition. VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1
SN54/74LS112A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54