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7. Circuit Operating Descriptions
7-1 Power
7-1-1 Comparsion between Linear Power Supply and S.M.P.S.
7-1-1 (a) Linear
Vout REGULATOR + Vp (Np) ­ + Vs ­ (Ns) + Vreg

Common power (Ex.120V 60Hz)

Fig. 7-1 Linear Power Supply Waveform/Description Vp

0

t

Input : Common power to transformer (Vp).

Fig. 7-2 Vs The output Vs of transformer is determined by the ratio of 1st Np and 2nd Ns. Vs = (Ns/Np) x Vp

0

t

Fig. 7-3 Vout

0

t

Vout is output (DC) by diode and condensor.

Fig. 7-4 Samsung Electronics 7-1

Circuit Operating Descriptions

Advantages and disadvantages of linear power supply 1) Advantages : Little noise because the output waveform of transformer is sine wave. 2) Disadvantages : OE Additional margin is required because Vs is changed (depending on power source). (The regulator loss is caused by margin design). ´ Greater core size and condensor capacity are needed, because the transformer works on a single power frequency. v Vout

Change by common power

Vreg

0 Regulator loss Fig. 7-5

t

7-1-1 (b) S.M.P.S. (Ringing Choke Converter methol)

Transformer (Np) (Ns) + + (Vp) (Vs) ­ ­ + + Vin Switch + Vs switch ­ I switch

Vout REGULATOR

Vreg

ON/OFF Control

Fig. 7-6 Terms 1) 1st : Common power input to 1st winding. 2) 2nd : Circuit followings output winding of transformer. 3) f (Frequency) : Switching frequency (T : Switching cycle) 4) Duty : (Ton/T) x 100

7-2

Samsung Electronics

Circuit Operating Descriptions

7-1-2 Circuit description [FLY-Back RCC(Ringing Choke Converter)] Control
7-1-2 (a) AC Power Rectification/Smoothing Terminal
1) PDS01, PDS02, PDS03, PDS04 : Convert AC power to DC(Full wave rectification). 2) PEF10 : Smooth the voltage converted to DC. 3) PLS01, PBS01 : Noise removal at power input/output. 4) PVA1 : SMPS protection at power surge input.

7-1-2 (b) SNUBBER Circuit : PDS11, PCD12, PER13, PRS13
Vswitch Inverted power by leakage inductance

dt

1) Prevent residual high voltage at the terminals of switch during switch off/Suppress noise. High inverted power occurs at switch (PQR11) off, because of the 1st winding of transformer : (V=-L1 xdi/dt. L1 : Leakage Induction) A very high residual voltage exist on both terminals of PQR11 because dt is a very short. 2) SNUBBER circuit protects PQR11 from damage through leakage voltage suppression by RC, (Charges the leakage voltage to PDS11, PER13, PCD12 and discharges to PRS13).

0 Toff

t

Fig. 7-7

7-1-2 (c) Driving circuit
When Vin supplied, driving current Ig occurs throuhg the PRR11. By this IC (=Hfe x Ig) occurs throug the PQR11 and the Vb is inducted to base winding coil NB of PQR11. By inducted Vb, Ib start flow and the PQR11 is saturated (S/W ON). Ib is constant and Ic increases in Proportion to time. After constant time passed Ib become to shortage and PQR11 is cut OFF (S/W OFF).

Fig. 7-8 Driving Circuit

Samsung Electronics

7-3

Circuit Operating Descriptions

7-1-2 (d) Feedback Control Circuit

A K

Fig. 7-9 Operation descriptions 1) Internal OP-Amp `+' base potential of PICS2 is 2.5V and external "-" input potential is connected with PRS33 and PRS34 to maintain Vout of 5.8V. 2) If load of 5.8V terminal increase (or AC inout voltage decrease) and Vout decrease over 5.8V, Then : PICS2 "R" potential decrease over 2.5V --> PICS2 A-K BASE Current decrease --> PICS2 A-K Current decrease --> PICS1 DIODE Current decrease --> PICS1 C-E Current decrease --> PICS1 C-E Voltage increase --> PICS1 F-B Voltage increase --> OUT DUTY increase TRANS Primary Cuttent Increase --> TRANS Primary Power increase --> Vout increase --> Vout maintain 5.8V - PRD31, PRD32 : Reduce 5.8V overshoot. - PRS32, PCS32 : Prevent PICS2 oscillation (for phase correction).

7-4

Samsung Electronics

Circuit Operating Descriptions

7-1-3 Internal Block Diagram
Internal Block Diagram

Smoothing Circuit Noise Removal (SNUBBER) Rectified Circuit Converter

3.3V Rectified Smoothing Circuit 5V Rectified Smoothing Circuit

3.3V Rectified VoltageCircuit 5V Rectified VoltageCircuit (x2)

Line Filter

Power TR Control Circuit Voltage Detection Circuit 12V Rectified Smoothing Circuit

Motor 12V 1 Port 12V Rectified VoltageCircuit

O U T P U T

Power IN (120V)

Fig. 7-10

Samsung Electronics

7-5

Circuit Operating Descriptions

7-2 RF
7-2-1 RIC1 (SP3723)
SP3723 is combined with Zoran Vaddis 6 as bipolar IC developed for DVD SERVO system. Main features include DVD waveform equalizing, CD waveform equalizing, focus error signal generation, 3-beam tracking error signal generation, DPD 1-beam tracking error, defect, MIRR output, Laser Power Control, etc.

7-2-1 (a) Basic Potentiometer
SP3723 Uses 4.5V to 5.5V and reference voltage is 1.65V.

7-2-1(b) RF signal
Fig. 7-11 shows the flow of signal generated by the pick-up. RF signal detected from pick-up is converted in to RF signal via RF interface and attennuators. A, B, C, D signals detected from pick-up are converted in to FE, TE, PI, CE, DEFECT signals.

Fig. 7-11

7-6

Samsung Electronics

Circuit Operating Descriptions

Fig. 7-12 shows the waveform-equalizing block diagram for the RF signal. RF signal from the pick-up is the input of RF equalizer module of RIC1 (SP3723). 102

102

J j
ATON ATOR

h
AIN

H
AIP

102 RF (FROM P/U)

K

RFSIN RF EQ

G

RFAC

Fig. 7-12

Samsung Electronics

FCCR

SIGR

CAR

7-7

Circuit Operating Descriptions

7-3 System Control
7-3-1 Outline
The main micom peripheral circuit is composed of 8M Flash Memory (ZIC3) for Microcode and data save, 2Kbit EEPROM (ZIC5) for permanent storage of data needed at power off, 64Mbit SDRAM (ZIC2) for temporary data read and write. The Micom (ZIC1 ; Vaddis 6E) mounted in main board analizes the key commands of front panel or instructions of remote control and controls the devices on board to execute the corresponding commands after initializing the devices connected with micom on board at power on.

7-3-2 Block Diagram
RIC1 RF AMP (SP3723) AIC1 D/A CONVERTER (PCM1742)

ZIC1 MPEG DECODER CPU (VADDIS 6E) DATA BUS

MICOM BLOCK

ZIC5 EEPROM (2K bit)

ZIC3 FLASH MEMORY 8 Mbit

ADDRESS

Fig. 7-13

7-8

Samsung Electronics

Circuit Operating Descriptions

7-4 Servo
7-4-1 Outline
SERVO system of DVD is Compoced of Focusing SERVO, Tracking SERVO, SLED Linked SERVO and CLV SERVO (DISC Motor Control SERVO). 1) Focusing SERVO : Focuses the optical spot output from object lens onto the disc surface. Maintains a uniform distance between object lens of Pick-up and disc (for surface vibration of disc). 2) Tracking SERVO : Make the object lens follow the disc track in use of tracking error signal (created from Pick-up). 3) SLED Linked SERVO : When the tracking actuator inclines outwardly as the object lens follows the track during play, the SLED motor moves slightly (and counteracts the incline). 4) CLV SERVO (DISC Motor Control SERVO) : Controls the disc motor to maintain a constant linear velocity (necessary for RF signal).

7-4-2 Block Diagram

36 35 38 37 1 2 5 6 7 4 3 10 11 8 9
LED POWER GND ZIC1(Vaddis 6E) ZIC1(Vaddis 6E) TM+ TM1 SP+ SP-

32 33

FIC1 (FAN8004)

15 8 3 48 11

OPEN CLOSE TM1 TM+ SP+ SP-

Fig. 7-14 Samsung Electronics 7-9

Circuit Operating Descriptions

7-4-3 Operation
1) FOCUSING SERVO
(1) FOCUS INPUT The focus loop is changed from open loop to closed loop, and the triangular waveform moves the object lens up and down (at pin 167 of ZIC1 during Focus SERVO ON.) At that time, S curve is input to pin 181 of ZIC1. PZ (pin 183 of ZIC1) signal, summing signal of PD A, B, C, D, is generated, and zero cross(1.65V) point occurs when S curve is focused and ABCD signal exceeds a preset,constant value. The focus loop is changed to closed loop, and the object lens follows the disc movement, maintaining a constant distance from the disc. (these operations are same in CD and DVD).

Pin 167 of ZIC1 (FOD)

Vref

Pin 181 of ZIC1 (FE)

Vref

Pin 183 of ZIC1 (AAF_PZ)

1.5V

Fig. 7-15 (2) PLAY When focus loop closes the loop during focus servo on, both pin 65 and pin 75 of SIC1 are controlled by VREF voltage (approx. 1.65V).

2) TRACKING SERVO
(1) NORMAL PLAY MODE OE For DVD Composite : The signal output from PD A, B, C, D of Pick-up, the tracking error signal (pin39 of RIC1) uses the phase difference of A+C and B+D in RIC1, and inputs to ZIC1. Then, it is output to ZIC1 pin 169 via digital equalizer, and applied to the tracking actuator through FIC3. Pin 69 of ZIC1 is controlled by VREF(approx. 1.65V) during normal play. Meanwhile, DVD repeats the track jump from 1 to 4 in inner direction at normal play (because data- read speed from disc is faster than data output speed on screen). ´ For CD, VCD Receive the signal output through E, F of Pick-up, from RIC1. The tracking error signal is similar to DVD.

7-10

Samsung Electronics

Circuit Operating Descriptions

(2) SEARCH Mode : Search mode : Fine seek,(Moving the tracking actuator slightly little below 255 track) and coarse search, moving much in use of sled motor. The coarse search will be described in sled linked servo and now, the fine seek is explained shortly. If the object lens is located near target, cut off the tracking loop and give the control signal as many as desired count to move the tracking actuator via ZIC1 pin 169 terminal(TRD).

3) SLED LINKED SERVO
· Normal play mode Move SLED motor slightly by means of PWM signal in ZIC1 pin 191, as the tracking actuator moves along with track during play. Control to move the entire Pick-up as the tracking actuator moves. · Coarse serach mode In case of long-distance search (such as chapter serach), ZIC1 uses MIRR and Global sense signal. Then, read ID and compute the existing track count after input of next track. If the existing track count is within fine seek range, tracking begins using fine seek.

4) CLV SERVO(DISC MOTOR CONTROL SERVO)
Input RF signal (from Pick-up) to ZIC1 pin 172, 173. Detect SYNC signal from RF in ZIC1, and output PWM signal to ZIC1 pin 189 for constant linear velocity.

Samsung Electronics

7-11

Circuit Operating Descriptions

7-5 DVD Data Processor
7-5-1 Outline
The Vaddis 6E(highly-integrated device) includes the full front-end disc controller, back-end decoder functions as well as the host control CPU. The principal off-chip components include the disc drive with its optical pickup, tray, sled and spindle drivers and motors, 16Mbits of flash EPROM, 64Mbits of SDRAM, and the audio Digital-to-Analog converters some applications. In case of general disc refresh, the memory is almost filled up periodically. It is because Write rate to memory after disc playback and signal process is faster than Read of A/V decoder. When the memory is filled, this status is reported by interrupt to main micom, which controls the servo to kick back the pick-up to the previous track after memorizing the last data read from disc until now. It takes some times to jump to the previous track and return to the original(jump location) again. The memory will have an empty space because A/V decoder reads out data of memory. When the memory has an empty space, where data can be processed and written and the pick-up correctly gets to the original location(before kick back location) again, it reads data again avoids the interrupt of data read previously. The basic operation repeats to perform as described above.

7-5-2 Block Diagram

Fig. 7-16 7-12 Samsung Electronics

Circuit Operating Descriptions

7-6 Video
7-6-1 Outline
ZIC1(A/V decoder with video encoder) diverges from the 27MHz crystal, then generates VSYNC and HSYNC. ZIC1(A/V decoder with video encoder) does RGB encoding, copy guard processing and D/A conversion of 8bit video data internally inputted from video decoder block by ZIC1. Video signal converted into analog signal is outputted via amplifier of analog part. Video data
CVBS CVBS Y C

CVBS

A/V Decoder Vaddis 6E With Video Encoder ZIC1

Y/R/V C/B/U CVBS/G/Y

Y Pb Pr

LOW PASS FILTER (6MHz)

6dB AMP & 75ohm Drive

Y C Y Pb

LA73054

Pr

Fig. 7-17 Video Output Block Diagram

7-6-2 NTSC/PAL Digital Encoder (VADDIS 6E ; Built in video encode)
ZIC1 inputted from pin 161 with 27MHz generates HSYNC and VSYNC which are based on video signal. ZIC1 is synchronous signals with decoded video signal and control the output timing of 8bit video signal of ITUR601 format. The separate signal is encoded to NTSC/PAL by control of MIC1. The above signals, which are CVBS (Composite Video Burst Synchronized)/G (GREEN)/Y [PIN158], Y (S_VIDEO)/R (RED)/Pr[PIN161] and C (S_VIDEO)/B (BLUE)/Pb [PIN162], are selectively outputted CVBS +S_VIDEO, RGB/Component by the rear switch. In Course of encoding, 8bit data can extend to 10bit or more. To convert the extended data to quantization noise as possible, ZIC1 adopts 10bit D/A converter. ZIC1 perform video en-coding as well as copy protection.

7-6-3 Amplifier (VIC1: LA73054)
VIC1 is 6dB amplifier. Based on CVBS signal, the final output level must be 2Vpp without 75ohm terminal resitance. Because the level of video encoder output is only 1.1Vpp, the level is adjusted with the special amplifier. When mute of pin 5 is high active, if the pin is floating and connecte to power, the output signal is never ouputted. CVBS, Y, C, R, Pb(B), Pr(R) outputted from video encoder are inputted to VIC1 (Pin 2, 8, 6, 16, 14). The signal to which gain is adjusted by amplifier is outputted from jack via 75ohm Resistance (VR11~VR16).

Samsung Electronics

7-13

Circuit Operating Descriptions

7-7 Audio
7-7-1 Outline
A/V decoder (ZIC1 ; Vaddis 6E) is supply to DATA 0 for 2-channel mixed audio output. The audio data transmitted from A/V decoder (ZIC1 ; Vaddis 6E) are converted into analog signal via audio D/A converter and outputted via post filter and amplifier. CD and VCD are outputted with only 2 channels audio data and transmit them to Data 0. If DVD of multichannel Source disc, if is downmixed and transmit them to Data0. If you want to listen to the multichannel output, you have to connect digital output with AC-3 amp or MPEG/DTS amp.

Mixed Audio Output (2-Channel) ZIC1 (Vaddis 6E) A/V Decoder DATA0 LRCK BCK AIC2 PCM1742KE D/A CONVERTER POST FILTER POST FILTER AMP AMP L R

Fig. 7-18 Audio Output Block Diagram

7-14

Samsung Electronics

Circuit Operating Descriptions

7-7-2 DVD Audio Output
Source Data Types : MPEG-1,-2, Dolby Digital, CD-DA, LPCM, WMA ZIC2 (LOCAL DRAM) HOST or DVD/CD INTERFACE ZIC1 (Vaddis 6E ; A/V DECODER)

AUDIO INPUT BUFFER Compressed Data WMA (MPEG, Dolby Digital), CD-DA, LPCM AUDIO DECODER (MPEG, DOLBY DIGITAL, CD-DA, LPCM, WMA

IEC-958/1937 OUTPUT PROCESS

IEC-958/1937 INTERFACE

RECEIVER or DECODER (IEC-958/1937)

2-Channel LPCM, Decoded Dolby Digital, Decoded MPEG, WMA

Uncompressed 16- or 24-bit LPCM samples at fs=44.1,48,96KHz 2-, 4, or 6CHANNEL OUTPUT PROCESS DIGITAL AUDIO INTERFACE AUDIO DAC

AUDIO OUTPUT BUFFER

Fig. 7-19 Audio Decoder and Output Interface Datapath

1) Compressed Data
The audio data inputted to ZIC1 (Vaddis 6E) A/V decoder is divided into compressed data and uncompressed data. It is compressed data that is compressed with multi-channel audio data such as Dolby digital, MPEG, DTS, WMA,etc. The compressed data inputted to ZIC1 (Vaddis 6E) is converted into the uncompressed data of 2, 4, and 6 channels through ZIC1 built-in audio decoder and is outputted to Data 0 through digital audio interface. The compressed data is transmitted to external AC-3 amplifier or MPEG/DTS amplifier as IEC-958/1937 transmission data format compressed by ZIC1 built-in IEC-958 output process.

2) Uncompressed Data
The uncompressed data is that data isn't compressed, so it is called CD-DA, LPCM data. The 2 channels data is converted through audio decoder 2-channel data and Data 0 and are outputted in digital audio interface.Via IEC-958 output process, they is transmitted to digital amplifier or AC-3/MPEG/DTS amplifier built in the external digital input source with IEC-958/1937 transmission format.

Samsung Electronics

7-15

Circuit Operating Descriptions

MEMO

7-16

Samsung Electronics