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TP2104

P-Channel Enhancement Mode
Vertical DMOS FETs
Features General Description
High input impedance and high gain This low threshold enhancement-mode (normally-off)
Low power drive requirement transistor utilizes a vertical DMOS structure and Supertex's
Ease of paralleling well-proven silicon-gate manufacturing process. This
Low CISS and fast switching speeds combination produces a device with the power handling
Excellent thermal stability capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent
Integral source-drain diode
in MOS devices. Characteristic of all MOS structures,
Free from secondary breakdown
this device is free from thermal runaway and thermally-
induced secondary breakdown.
Applications
Logic level interfaces - ideal for TTL and CMOS Supertex's vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
Solid state relays
low threshold voltage, high breakdown voltage, high input
Analog switches
impedance, low input capacitance, and fast switching
Power management
speeds are desired.
Telecom switches

Ordering Information
Package Options RDS(ON) VGS(th)
BVDSS/BVDGS
Device (max) (max)
TO-236AB (SOT-23) TO-92 (V)
() (V)
TP2104 TP2104K1-G TP2104N3-G -40 6.0 -2.0
-G indicates package is RoHS compliant (`Green')

Pin Configuration

DRAIN

DRAIN

SOURCE
SOURCE

Absolute Maximum Ratings GATE
GATE
Parameter Value TO-92 (N3) TO-236AB (SOT-23) (K1)
Drain-to-source voltage BVDSS Product Marking
Drain-to-gate voltage BVDGS SiTP YY = Year Sealed
Gate-to-source voltage