Text preview for : tmp68303f-16_775.pdf part of Various tmp68303f-16 775 . Electronic Components Datasheets Various tmp68303f-16_775.pdf
Back to : tmp68303f-16_775.pdf | Home
TMP68303F-16 (1/3)
IL22
**********
C-MOS 16-BIT MICRO PROCESSOR
--TOP VIEW--
75
70
65
60
55
51
VDD(+5V)
GND
76 VDD(+5V) 50
80
45
85
40
GND GND
90
35
95
30
VDD(+5V)
GND
100 VDD(+5V) 26
1
5
10
15
20
25
(VDD = +5 V)
PIN PIN PIN PIN PIN
I/O SIGNAL I/O SIGNAL I/O SIGNAL I/O SIGNAL I/O SIGNAL
No. No. No. No. No.
1 I/O A19 21 I/O D1 41 I/O M11/P11 61 I/O LDS 81 I/O A1
2 I/O A20 22 I/O D0 42 I/O M10/P10/ 62 I/O R/W 82 I/O A2
TOUT4
3 I/O A21 23 I/O CTS0/P21 63 -- GND 83 I/O A3
43 I/O M03/P03
4 I/O A22 24 I/O RTS0/P20 64 I CLK 84 I/O A4
44 I/O M02/P02
5 I/O A23 25 -- VDD 65 O TOUT2 85 I/O A5
45 I/O M01/P01
6 I/O D15 26 O TXD1 66 O TOUT1 86 I/O A6
46 I/O M00/P00/
7 I/O D14 27 O TXD0 TOUT3 67 I TIN 87 I/O A7
8 I/O D13 28 I RXD1 47 O IACK2 68 O BG 88 -- GND
9 I/O D12 29 I RXD0 48 O IACK1 69 I/O BGACK 89 I/O A8
10 I/O D11 30 I BCLK 49 O IACK0 70 I/O BR 90 I/O A9
11 I/O D10 31 I/O DTEND 50 -- VDD 71 I/O DTACK 91 I/O A10
12 I/O D9 32 O DACK2 51 I INT2 72 I/O HALT 92 I/O A11
13 -- GND 33 O DACK1 52 I INT1 73 I/O RESET 93 I/O A12
14 I/O D8 34 O DACK0 53 I INT0 74 I/O BERR 94 I/O A13
15 I/O D7 35 I DREQ2 54 O CAS/CS1 75 -- VDD 95 I/O A14
16 I/O D6 36 I DREQ1 55 O RAS/CS0 76 I NOR/EMU 96 I/O A15
17 I/O D5 37 I DREQ0 56 I/O IPL2 77 I BGIN 97 I/O A16
18 I/O D4 38 -- GND 57 I/O IPL1 78 I/O FC2 98 I/O A17
19 I/O D3 39 I/O M13/P13 58 I/O IPL0 79 I/O FC1 99 I/O A18
20 I/O D2 40 I/O M12/P12 59 I/O AS 80 I/O FC0 100 -- VDD
60 I/O UDS
TMP68303F-16 (2/3)
5 6 INPUT
A23 D15
4 7 BCLK ; BAUD RATE CLOCK
A22 D14
3 8 BGIN ; BUS GRANT
A21 D13
2 9 CLK ; CLOCK
A20 D12
1 10 CTS0 ; CLEAR TO SEND
A19 D11
99 11 DREQ0 - 2 ; DMA REQUESTS
A18 D10
98 12 INT0 - 2 ; INTERRUPT REQUESTS
A17 D9
97 14 NOR/EMU ; MODE SELECT
A16 D8
96 15 RXD0, 1 ; RECEIVE SERIAL DATA
A15 D7
95 16 TIN ; TIMER INPUT
A14 D6
94 17
A13 D5
93 18 OUTPUT
A12 D4
92 19 BG ; BUS GRANT
A11 D3
91 20 CAS ; COLUMN ADDRESS STROBE
A10 D2
90 21 CS0, 1 ; CHIP SELECTS
A9 D1
89 22 DACK0 - 2 ; DMA ACKNOWLEDGE
A8 D0
87 IACK0 - 2 ; INTERRUPT ACKNOWLEDGE
A7
86 34 M00 - 03, 10 - 13 ; MOTOR CONTROL
A6 DACK0
85 33 RTS0 ; REQUEST TO SEND
A5 DACK1
84 32 RAS ; ROW ADDRESS STROBE
A4 DACK2
83 49 TOUT1 - 4 ; TIMER OUTPUTS
A3 IACK0
82 48 TXD0, 1 ; TRANSFER SERIAL DATA
A2 IACK1
81 47
A1 IACK2
46 INPUT/OUTPUT
M00/P00/TOUT3
29 45 A1 - 23 ; ADDRESS BUS
RXD0 M01/P01
28 44 AS ; ADDRESS STROBE
RXD1 M02/P02
23 43 BERR ; BUS ERROR
CTS0/P21 M03/P03
53 42 BGACK ; BUS GRANT ACKNOWLEDGE
INT0 M10/P10/TOUT4
52 41 BR ; BUS REQUEST
INT1 M11/P11
51 40 D0 - 15 ; DATA BUS
INT2 M12/P12
37 39 DTACK ; DATA TRANSFER ACKNOWLEDGE
DREQ0 M13/P13
36 66 DTEND ; DMA FORCED END / TRANSFER END
DREQ1 TOUT1
35 65 FC0 - 2 ; FUNCTION CORDS
DREQ2 TOUT2
30 HALT ; HALT
BCLK
64 31 IPL0 - 2 ; INTERRUPT CONTROLS
CLK DTEND
77 27 LDS ; LOWER DATA STROBE
BGIN TXD0
76 26 P00 - 03 ; PORT 0
NOR/EMU TXD1
67 68 P10 - 13 ; PORT 1
TIN BG
58 54 P20, 21 ; PORT 2
IPL0 CAS/CS1
57 55 RESET ; RESET
IPL1 RAS/CS0
56 24 R/W ; READ/WRITE
IPL2 RTS0/P20
59 UDS ; UPPER DATA STROBE
AS
60 69
UDS BGACK
61 70
LDS BR
62 71
R/W DTACK
80 72
FC0 HALT
79 73
FC1 RESET
78 74
FC2 BERR
P00-03
P10-13
INT0-2 IACK0-2 RXD0, 1 TXD0,1 CTS0 RTS0 BCLK RAS CAS M00-03 M10-13 P20, P21
53-51 49-47 29, 28 27, 26 23 24 30 55 54 46-43 42-39 46-39
24,23
70
BR
68
BG RAS/CAS PHASE GEN.
UART UART CIRCUIT
69 INTERRUPT GENERATION
PRIORITY CIRCUIT
BGACK REQUEST A0-A23
DECISION
RECEIVE
CIRCUIT BAUD BAUD ALTERNATE 81-87
CIRCUIT
RATE RATE REGISTER 89-99
REFRESH 1-5
GENERATOR GENERATOR
TIMER
IPL0-2
PHASE GEN. D0-D15
10-BIT PORT
CIRCUIT 22-14
INTERRUPUT PRIORITY
ACKNOWLEDGE 12-6
RANKING
CORRESPONDENCE PRESCALER
CIRCUIT ALTERNATE AS 59
CIRCUIT REGISTER UDS 60
PARALLEL LDS 61
I/F R/W 62
INTERRUPT SERIAL I/F DRAM STEPPING
CONTROLLER CONTROLLER MOTOR
INTERRUPT CS0 FC0-2
CONTROLLER
REQUEST INNER BUS 80-78
CORE
INTERFACE
(68HC000)
INTERRUPT IINTERRUPT
PROCESSOR
REQUEST BR, BG REQUEST
ADDRESS
BGACK TIMER
DECODER DMA CONTROLLER
DTACK WAIT
CONTROL MEMORY ORIGIN TIMER/
MEMORY MEMORY REGISTER COUNTER
BERR REGISTER REGISTER
73 TIMER/
RESET MEMORY END COUNTER
TIME OUT
72 SUPERVISION REGISTER
HALT DATA DATA TIMER/
CIRCUIT TRANSFER COUNTER
TRANSFER
76 REGISTER REGISTER DATA TRANSFER
PRESCALER
PRESCALER
NOR/EMU REGISTER TIMER/
COUNTER
64 CS
CLK
GENERATION TIMER/
58-56 CIRCUIT MEMORY BUS CYCLE DATA TRANSFER COUNTER
IPL0-2 COUNTER GENERATION CIRCUIT COUNTER
77
BGIN
55 54 74 71 37-35 34-32 31 67 66, 65, 46, 42
TMP68303F-16(3/3)
CS0 CS1 BERR DTACK DREQ0-2 DACK0-2 DTEND TIN TOUT1-4