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SN54/74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be DUAL JK NEGATIVE
accepted. The logic level of the J and K inputs may be allowed to change when EDGE-TRIGGERED FLIP-FLOP
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred LOW POWER SCHOTTKY
to the outputs on the negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 632-08
14
Q Q 1
5(9) 6(8)
CLEAR (CD) 4(10) N SUFFIX
TO SET (SD)
PLASTIC
OTHER K CASE 646-06
FLIP-FLOP 14
J 2(12)
3(11) 1
13
CLOCK (CP)
D SUFFIX
SOIC
14
1 CASE 751A-02
ORDERING INFORMATION
MODE SELECT -- TRUTH TABLE
SN54LSXXXJ Ceramic
INPUTS OUTPUTS SN74LSXXXN Plastic
OPERATING MODE SN74LSXXXD SOIC
SD CD J K Q Q
Set L H X X H L
Reset (Clear) H L X X L H
*Undetermined L L X X H H LOGIC SYMBOL
Toggle H H h h q q
Load "0" (Reset) H H l h L H
4 10
Load "1" (Set) H H h l H L
Hold H H l l q q
SD 11 SD
* Both outputs will be HIGH while both SD and CD are LOW, but the output states 3 J Q 5 J Q 9
are unpredictable if SD and CD go HIGH simultaneously.
13 CP CP
H, h = HIGH Voltage Level
L, I = LOW Voltage Level 2 K CD Q 6 12 K C Q 8
X = Don't Care D
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition. 1
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-1
SN54/74LS114A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54